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July 2001

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Subject:
From:
Tony Steinke <[log in to unmask]>
Reply To:
Tony Steinke <[log in to unmask]>
Date:
Fri, 27 Jul 2001 09:35:09 -0400
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Daan,
With a .3mm(.012in.) finish h/s and a .6mm(.024in.) clearance seems to be
very
tight considering the initial drill h/s to achieve a .3mm finish h/s would
probably
have been around a .015-.016, which would only leave you with about a
.004/.005 annular ring. It appears that your supplier failed to perform a
DRC
(design rule check) when panelizing the board for production, which would
have raised a red flag. Also you mentioned that the board is
20*15cm(7.87*5.90in.)
is the finish size, but actually was probably built on an 18x24in. panel for
multiple up processing(4 boards per panel). Another question is how many
layers is this design. If it is more than 8-10 layers, material shrinkage
during
manufacturing plays a vital role also.
Tony Steinke
Circuit Technologies Inc.
[log in to unmask]
----- Original Message -----
From: d. terstegge <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, July 27, 2001 4:37 AM
Subject: [TN] Clearance area around holes


Hi Technet,

Here's a question for the bare board experts out there:

One of our pcb-suppliers had rejects on a complete batch of our boards
because the clearance between the via's and the surrounding copperplane was
so small that it resulted in short circuits.
The holes were designed 0.3 mm (finished hole size) and the openings in the
copperplane were 0.6 mm, leaving only a small clearance area. The board
measures about 20*15 cm.
What do you think, is a board like this manufacturable for a decent board
shop, or is it really that difficult?  Could you give me a typical value for
the minimum clearance around the finished-hole that board vendors need ?

Best regards,

Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net

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