As far as I know, the theoretical calculations have never matched the
actual board. Probably a combination of measurement techniques, raw
material variation and manufacturing process.  As I recall, 5% discrepancy
between theoretical and actual was usual.

I also think that the plane/trace relationship will dominate at this
dielectric spacing. I would focus more on the L2/L3 and L4/L5 spacing.

The other issue is: how long of an isolated reduction in trace width or
height will give a spike in impedance?

If I were looking to understand this in depth, I would start with the
metrology. If your measurements are in question, forget the rest. Rigorous
metrology is the key to impedance testing. The Polar software is a good start.

Steve

  At 05:33 AM 7/17/2001, tech wrote:
>I have a 6 layer design with layers 2 and 5 being planes and 3 and 4
>signals. In this particular case , due to overall thickness and outer
>layer impedance requirements we have .010 from the planes to the signals
>and .035 between the signals. 1 Oz. copper and finished lines at .006.
>My impedance software ( Polar CITS25) is giving a number of 65.02 ohms
>but the actual results we're getting are all at the 72+ ohm range.We do
>many impedance designs and have not seen a discrepency like this. The
>.035 dielectric between the signals is 5 pieces of 7628 which is an
>unusually high amount of prepreg for us and the .010 from planes to
>signals are cores. All 140Tg FR4. Can the high thickness (resin content)
>of prepreg be creating the problem ? Sections on the coupons are very
>close to design so we don't appear to have a process issue.
>  Any input appreciated.
>Paul Greene
>
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