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July 2001

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Subject:
From:
Mark Hargreaves <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 11 Jul 2001 14:06:20 -0400
Content-Type:
text/plain
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text/plain (95 lines)
Hi All,
If there are any holes (dimensioned) in the PCB, it seems that copper
feature location is controlled by hole to pad (annular ring) tolerance.
I've often seen board (or panel) fiducials used with reference dimensions to
allow assemblers to fine tune their setups to match the actual PCB.
I think that pattern to pattern tolerance is most important on a component
pad pattern, or adjacent traces.  And over those smaller distances, the
0.05% tolerance is probably very acceptable.  I think our photoplotter spec
was "positional accuracy" of about 0.00025" over a 24" x 34" sheet.  Seems
that twice that should equal the feature to feature spec of the plotter.
Of course, lots can happen to that image after it leaves the plotter.

Regards,
Mark Hargreaves


        -----Original Message-----
        From:   d. terstegge [SMTP:[log in to unmask]]
        Sent:   Wednesday, July 11, 2001 11:37 AM
        To:     [log in to unmask]
        Subject:        Re: [TN] Pattern to Pattern Tolerance

        Hi Scott,

        About a year ago I asked the same question on Technet and I was
suprised that I received no answers. I was even more surprised that most of
our pcb-suppliers could not give me any specification for feature to feature
tolerance, in spite of the fact that this is can be an extremely important
parameter for assembly (especially for large boards with fine pitches).
        Finally I found out that 0.05% is a typical value for pattern to
pattern tolerance, which means that there can exist a 0.15 mm tolerance over
a 300 mm distance !!
        Stretch and shrink can occur during manufacturing of the board, and
is not only caused by artwork imaging or geber plotting.

        Kind regards,

        Daan Terstegge
        SMT Centre
        Thales Communications
        Unclassified mail
        Personal Website: http://www.smtinfo.net

        > ----------
        > From:         Buscomb, Scott[SMTP:[log in to unmask]]
        > Reply To:     TechNet E-Mail Forum.;Buscomb, Scott
        > Sent:         Monday, July 09, 2001 6:07 PM
        > To:   [log in to unmask]
        > Subject:      [TN] Pattern to Pattern Tolerance
        >
        > I am looking for the standard industry locational tolerance of
copper
        > feature to copper feature on a single sided PCB. Since PCB
fabrication is
        > a
        > photographic process, I am assuming it is a function of gerber
plotter and
        > artwork imaging.
        > TIA,
        >
        > Scott Buscomb
        >
        >
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