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July 2001

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From:
"d. terstegge" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 11 Jul 2001 17:36:32 +0200
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Hi Scott,

About a year ago I asked the same question on Technet and I was suprised that I received no answers. I was even more surprised that most of our pcb-suppliers could not give me any specification for feature to feature tolerance, in spite of the fact that this is can be an extremely important parameter for assembly (especially for large boards with fine pitches).
Finally I found out that 0.05% is a typical value for pattern to pattern tolerance, which means that there can exist a 0.15 mm tolerance over a 300 mm distance !!
Stretch and shrink can occur during manufacturing of the board, and is not only caused by artwork imaging or geber plotting.

Kind regards,

Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net 

> ----------
> From:         Buscomb, Scott[SMTP:[log in to unmask]] 
> Reply To:     TechNet E-Mail Forum.;Buscomb, Scott
> Sent:         Monday, July 09, 2001 6:07 PM
> To:   [log in to unmask] 
> Subject:      [TN] Pattern to Pattern Tolerance
>
> I am looking for the standard industry locational tolerance of copper
> feature to copper feature on a single sided PCB. Since PCB fabrication is
> a
> photographic process, I am assuming it is a function of gerber plotter and
> artwork imaging.
> TIA,
>
> Scott Buscomb
>
> --------------------------------------------------------------------------

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