Hi Matthew,
(hope this isn't too long winded)..
UL, CSA, VDE, TUV, and the newer CE mark are not easily attainable... If you
have ever had the experience of designing to these agency approval
standards, they have more strict requirements than the standards for most
board designs...
The main concern is SAFETY. Shock hazard and Fire Hazard. The use of a
standard, or guideline can make your life easier. If you can design to the
min. spacing requirements of the guidelines you should have no trouble
getting agency approval. If you go below the minimum spacing, they will
require you to test the board to prove it doesn't burn or present a
catastrophic failure or present a shock hazard to the end user of the
device. The agency will usually provide you with their requirements or
guidelines for spacings at specific voltages. (These spacings are typically
derated 50% for margin.) The minimums can be broken... BUT the testing gets
more expensive. Its better to follow the guidelines like they were rules and
then the testing is minimal and approval is quick.
As an added thought - I have designed boards with a high pot requirement of
4KV and only had a gap of 90 mils. Less than 86 mils with process tolerances
and we would see failures in product. That is something we were forced into
by physics...and the need to make it smaller and smaller.... Cleanliness of
the surface of the boards became critical! Contaminants can create a ionic
path for break over voltages to breach. Sharp corners on traces are
typically where the arcs wanted to go... We did a lot of testing to find out
the absolute minimums we could live with... Save yourself the headaches if
you can avoid it. Follow the guidelines.
In the case of Transistor leads, Some are approved by VDE and some are not.
Check the specs on the parts. If they are approved then you need not worry
about the spacing issues of the component. The board is a different matter.
The materials that are present on the surface of the board or the
contaminants present due to poor or incomplete cleaning of fluxes or
sponofiers and rinses can degrade the surface resistance of the board. The
agency specify CREEP over the surface of the board and CLEAR through the
air. Different requirements entirely. Also they differentiate between
spacings with the presence of contaminants or 'dirt' and conformal coated
electronics that are protected from 'dirt' or contaminants. Read the specs
carefully. They will make your life a lot easier. That way you will actually
get your product to market on time instead of having to explain why you are
still in testing with UL because they have a problem with your product
failures...
- Bill
Bill Brooks
PCB Design Engineer
DATRON WORLD COMMUNICATIONS INC.
3030 Enterprise Court
Vista, CA 92083
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
mailto:[log in to unmask]
IPC Designers Council, San Diego Chapter
http://www.ipc.org/SanDiego/
http://home.fda.net/bbrooks/pca/pca.htm
-----Original Message-----
From: Matthew Lamkin
[mailto:[log in to unmask]]
Sent: Friday, July 27, 2001 3:07 AM
To: [log in to unmask]
Subject: [DC] High voltage spacing and transistor pinouts.
Help, I got an engineer moaning at me for an explanation of one of my std
design rules...
When designing a board layout, with high voltages on, I have to apply
spacing rules dependant upon the
voltage, I.E. if its at 400V I use approximately a 4mm gap between tracks.
However, the same tracks that are at 400v can come to a TO220 transistor
pads, which would be a lot closer, especially
when the transistor leads enter the body of the transistor, seemingly
negating any spacing rule that is applied on the board layout?
This has come about when I told him that "he cant put them tracks 2 thick
under that 10mm pitch cap its at 400v!" (or words to that effect).
Can someone explain the voltage/spacing rule to me sot I can pass it on.
Also, what effect does having a solder mask have on this? I always have
solder mask so any non mask problems would not arise.
Many thanks - Matthew Lamkin.
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