Hello Designers,

On my last project there were two different potentials on
the GND and VCC Power plane. The Board was a 8 layer one. The stackup
was
1 - Signal
2 - Signal
Core between
3 - Split GND Plane
4 - Signal
Core between
5 - Signal
6 - Split VCC Plane
Core between.
7 - Signal
8 - Signal
On Layer 3 there is a polygon (8500000 square mils) of one potential
that overlaps
with a polygon on Layer 6 which has a different potential.
Do you think it is possible to couple enough noise with this to bring a
programmable
Logic device to a undefined state ?

Regards,
Florian Pitzl

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