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Subject:	Re: Separation Guidelines For PCB Traces Running Under Components
From:	Charles Lawson <[log in to unmask]>
Reply To:	TechNet E-Mail Forum.
Date:	Fri, 8 Jun 2001 08:22:32 -0400
Content-Type:	text/plain
Parts/Attachments:	text/plain (50 lines)

James,

I would be most concerned about the minimum electrical spacing between the
trace and the external component lead/termination.

IPC-A-610C, Appendix A, gives guidelines for minimum electrical conductor
spacing that are taken from IPC-2221 (2/98), paragraph 6.3.  I suggest
looking at Table 6-1 and paragraphs 6.3.6 and 6.3.7  Also consider the Note
in Section 9.2 of IPC-A-610C, that solder resist coatings should not be
considered as an "insulator or insulative material".

Charles Lawson
Product Assurance
General Dynamics Advanced Technology Systems


>Date:    Thu, 7 Jun 2001 15:09:01 -0400
>From:    "Riling, James J" <[log in to unmask]>
>Subject: Separation Guidelines For PCB Traces Running Under Components
>MIME-Version: 1.0
>Content-Type: text/plain
>
>Several of my companies PCB's have traces running under components.  For
>Horizontal and Vertical Axial Leaded Components IPC-A-610 specifies a
>minimum distance for the components to be above the board surface.  Are
>there any other "separation" guidelines for Traces Running Under Leaded
>Components?  In addition, we also have PCB's w/ traces running under surface
>mount chip resistors and capacitors.  Are there any "separation" guidelines
>for surface mount?  In particular, is there a guideline for the minimum
>width of the ceramic substrate for a SM Chip Resistor or the insulation
>characteristics of the substrate?
>
>Any help would be greatly appreciated.
>
>James J. Riling
>Hardware Validation Engineer
>Union Switch & Signal Inc.
>Phone:  (412)688-2926  Fax:  (412)688-2398
>Email:  [log in to unmask]

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