Hei MoonMan

Looking at the pictures I think I see two problems.
- Picture 1: Overview of the device. Am I right that this is kind of power electronics? The areas with the problem seem to me like arrays of FET or bipolars.
First impression is thermal overstress with a main path running right over the array and heat spreading effects along the edge.
- Pictures 2,3: I couldn't find out where on pic.1 this area is. Looks like ESD.
- Pictures 4,5,6: The details seem to confirm the first impression of pic.1. Thermal overstress with pretty violent destruction of the semiconductor structure.

Naturally this it not a real analysis, just first impressions. Tho know more one needs a thorough failure analysis which tends to be a quite big thing (at least in our place but that might be different in other labs).

Have a great day

Gunter

Guenter Grossmann

Swiss Federal Institute for Materials Testing and Research EMPA
Centre for Reliability
8600 Duebendorf
Switzerland

Phone: xx41 1 823 4279
Fax :      xx41 1823 4054
mail:     [log in to unmask]

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