Hi all,
am a little late, don't know much about GaAs cracking once the chips are soldered. We have been using GaAs thinned chips for many years, Au/Sn vacuum soldered on CuMo or CuW heatspreaders. We use large chips and small, extremly hot and low power, digital and RF, on LTCC or thinfilm, shortly, a whole family of designs, but we have never had crack problems. The crystal structure of GaAs is such that a starting crack could easily travel across whole chip, but occasionally we have had just a few incidents in prototyping work. Therefore, it seems as once you have mounted KGD there is little crack risk. The very crack risk seems to occur before soldering rather than afterwards, namely a)the sensitivity to edge damage from tweezer handling or improper p-p tools and b)if you have whole line of etched ground vias on backside. The later acts like perforation and could easily cause breakage of parts of the chip or even whole chip. In our CAD guidlines we avoid to place vias in long ro!
ws.
In the whole, GaAs chips seem to be tougher than expected. For instance, I read an article, probably from Diemat (silverglass), about mounting 10x10 mm GaAs chips on copper(!) carriers, and they did not crack even after vigorous tempcycling and power switching. If you have a scrap GaAs wafer, take it and bend it by hand, you'll be surprised when you see what it can withstand (not very scientific test, just gives an idea, people think wafers are so fragile)
There are some interesting diffs between Si and GaAs:
Atomic weight Si=28 GaAs=144
Crystal structure Si=Diamond GaAs=Znblende
Density Si=2.3 GaAs=5.3
CTE Si=2.6 GaAs=6.7
Spec heat Si=0.7 GaAs=0.3
Lambda Si=1.5 GaAs=0.5
Thermal diffus. Si=0.9 GaAs=0.2
As you can see they are very dissimilar. I think one of the most important factors for power designing is to notice that GaAs is a bad heat conducting material, especially in bilateral orientation. Our engineers use to talk about GaAs as 'frigolite'. You have to thin the substrates and use heat vias near the transistor fingers, spread the heat laterally by means of thick metal bridges etc. Whole wizards toolbox, speaking highpower and RF. If you sink heat shortest possible way to heatspreader and carrier, you minimize chip thermal expansion. And the solder joint must be voidfree, except for micronlarge bubbles that will always occur.
My 2 1/2 p
Ingemar Hernefjord
Ericsson Microwave Systems
-----Original Message-----
From: Misner, Bruce [mailto:[log in to unmask]]
Sent: den 13 juni 2001 16:32
To: [log in to unmask]
Subject: Re: [TN] X-ray Images
Steve,
Maybe it's just me, but, while I can see the 2 x-sections, I don't have the
x-rays.
Earl,
The die size and assembly process would be very helpful (attachment in
vacuum?). While GaAs is a brittle material it will bend in 1.5 mil
thickness' which is probably from TCE mismatch (obviously on larger die
since the mismatches are not large) and I would think vac pressure could
contribute as Steven suggested. Have you cross sectioned known good die to
see if they are warped also? If the attachment voiding is significant, you
might consider Ag epoxy attachment. With a thin bond line on a good
Cu/Invar heat spreader like you have, 98% attachment with epoxy vs 60-70%
with eutectic may be thermally acceptable, depending, of course, on your
application. Also, you can check for cracks with a dye penetrant or often
by slowly running a felt tip pen (like a red Flair) across the die while
under a microscope. Capillary action will pull the ink into the crack(s) and
obviously show it.
Good Luck,
Bruce Misner
> ----------
> From: Stephen R. Gregory[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;[log in to unmask]
> Sent: Wednesday, June 13, 2001 8:58 AM
> To: [log in to unmask]
> Subject: [TN] X-ray Images
>
> Hey ya'll!
>
> Earl has one more picture up, it's 4 x-ray images of the device showing
> voiding under the die or thin eutectic. Go to:
>
> http://stevezeva.homestead.com/index.html
>
> Since he can't post from where he's at, he's asked me to pose the
> following
> question:
>
> "How much flexibility does GaAs have and is the current eutectic contour
> too
> much (as in x-sections on Steve's site)? Can these die crack under
> additional
> thermal stress and cause the catastrophic failures shown in other images?"
>
>
> -Steve Gregory-
>
>
>
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