de nada /Inge
-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: den 28 maj 2001 14:37
To: TechNet E-Mail Forum.; Ingemar Hernefjord (EMW)
Subject: Re: [TN] Ionic contamination limit for PWA with 0402 sized
components
Wow! Thanks for pointing out my error, Ingemar, 50 V/mm of course !!!!!
Mea Culpa :-(
Brian
"Ingemar Hernefjord (EMW)" wrote:
>
> 50V/um!! Are you really in the right magnitude, it's a lot!
> Ingemar
>
> -----Original Message-----
> From: Brian Ellis [mailto:[log in to unmask]]
> Sent: den 28 maj 2001 11:48
> To: [log in to unmask]
> Subject: Re: [TN] Ionic contamination limit for PWA with 0402 sized
> components
>
> Chuck
>
> It sounds as if you may either have to clean (with or without coating)
> or seriously qualify the most suitable "no-clean" chemistry. These
> chemistries are not born equal and some are very much less equal than
> others. If the criterion of choice for it is for easiest soldering, then
> this is where I would point the finger.
>
> You have two problems here: how to save the assemblies already made and
> how to prevent future ones from doing the same. The latter will be the
> easier, but a lengthy and costly qualification procedure of materials
> and processes will be very necessary.
>
> Removing aged "no-clean" flux will not be a joyride, but I think it is
> the only course you have to save what you already have. A very energetic
> and long spray wash in, say, a Vigon A200 solution at 55°C, followed by
> adequate DI rinsing would probably be your best bet. I'd aim for an
> ionic contamination level of <0.25 ug/cm2. That alone may be sufficient,
> but I'd do a practical test at at least 35°C and 95% (try the N.
> Queensland tropical rain forests or take a holiday in Port Moresby!). If
> not, then a conformal coating may become necessary, after cleaning.
>
> Conformally coating boards with your current contamination level would
> probably be totally disastrous. All it would do is to delay the onset of
> problems as the moisture penetrated the coating.
>
> What is most likely happening is that you are having electrolytic
> conduction, possibly without even dendrites forming. This is sufficient
> to "change bits" in a hi-Z RAM circuit, as the charge is very small for
> it to leak below the zero threshold. A common mistake in PCB design with
> such components is to "clump" traces together, forming longish parallel
> paths with very narrow spacings. It is much better to space them as
> widely as possible to fill the available space (some CAD routers will do
> this automatically, if you tell them to). Remember that the danger does
> not lie so much in adequate spacing as in the critical voltage
> gradients, which should always be as low as possible. It may help to
> place all the critical paths in the inner layers, alternating, for
> example, tracks between layers 2 and 3. This reduces the risk of
> crosstalk, as well, but it minimises the risk on the critical outer
> layers. This is something which we may face increasingly with HDIS
> circuits, as soon as the voltage gradient exceeds, say, 50 V/um.
>
> Hope this helps.
>
> Brian
>
> Chuck Mays wrote:
> >
> > I've checked the technet archive and have not found a similar problem, so
> > here goes.
> >
> > I have a problem with a small mobile product that is failing in field
> > trials. One area we have considered is a combination of RH and the level
> > of ionic contamination affecting high impedance areas of the PWA to cause
> > the problem. (The problem exhibits itself as a RAM corruption and the S/W
> > engineers are busily making sure it isn't their problem.)
> >
> > An external lab checked a sample of the PWA's using the Omega method and
> > found the average level to be about 18 ug/sq.in. (I'm aware that 10
> > ug/sg.in. is the recommended limit.) The PWA uses 0402 sized resistors and
> > is the finest pitched assembly that the manufacturer in China who builds
> > this and other boards for us uses. A no clean process is used. The other
> > products built for us by this manufacturer are OK in terms of ionic
> > contamination and field performance.
> >
> > Most of the failures in field trials have occurred not too far from the bay
> > in one of the suburbs of Sydney where the field trials are in progress.
> > The temperature is not high (15 - 20 degrees C), but we are now in the
> > rainy season. One day, when it rained in the suburb nearer the bay, and
> > not in the other field trial areas, 6 of the field trial units failed in
> > the one area.
> >
> > My questions are:
> > 1. Does anyone have experience that indicates that the 10ug/sq.in. level
> > for ionic contamination is OK for PWAs that use 0402 sized components? Or
> > does experience indicate that a lower level is more appropriate and if so,
> > what level? (It don't know the exact pitch of this board, but am waiting
> > for the answer.)
> > 2. Is it possible to determine an impedance above which one should be
> > concerned with a level of ionic contamination for a given voltage?
> > 3. If it turns out that for this design, RH and the level of ionic
> > contamination are causing the problem, can the situation be improved by
> > conformally coating the board or areas of the board? (If so, can someone
> > please point me to the applicable standards for conformal coating? Thanks.)
> >
> > Best Regards,
> >
> > Chuck Mays
> >
> > Invetech Operation Pty Ltd
> > [log in to unmask]
> >
> > Tel 613 9211 7700
> > Fax 613 9211 7702
> >
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> >
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