Dave,

Not to add an additional load onto your shoulder, but don't forget to derate
the board if the operating enviroment has temperature cycles, humidity
cycles, or high humidity. Long-term exposure to these environments will lead
to small delams, which will reduce the ability of the board to withstand
dielectric breakdown.

Best Regards
Craig

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Brocious, Dave A
Sent: Friday, May 25, 2001 2:22 PM
To: [log in to unmask]
Subject: [TN] PWB Testing


> Hello All,
>       This Question was raised by one of our engineers. Please copy
> [log in to unmask] with your response. Thank you in advance for your
> inputs.
>
>       We need to rate and to test a board used at High Voltages.
>
>       A Printed Wiring Board (IPC-4101/42) is occasionally subjected to DC
> voltages around 3.5kV for a time duration of about one hour. Clearances
> and geometry have been selected per applicable standards. The finished
> assembly receives a heavy coating of an insulating polymer over all
> portions subjected to High Voltages.
>  The board is used in an application where any breakdown would be
> unacceptable.
>
>       The bare-board drawing presently specifies a voltage rating of 100V
> DC except for the HV portion(s) which are rated at 4500 VDC.
>       A PWB manufacturer has stated that this requires them to perform
> Hipot tests at 2 x 4500VDC or 9kVDC. This level is excessive, in our
> estimation.
>
>
>  What we need to know is:
>
>  1). If portions of the PWB are rated for 4500 VDC, what testing and what
> voltage levels should be used? It is desirable to test every board, in
> addition to test coupons, due to the critical nature of the application.
>
>  2). What level of current limiting should be used? It is thought by us
> that some Hipot testers may only indicate a test failure once the current
> level reached a few milliamperes and this level may be damaging to the
> PWB.
>
>
>  Thanks in advance.
>
>
>  Sandor
>
>

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