Kelly,
I would consider the orientation of devices to wave. This has the greatest
effect on wave soldering SMT's on bottom side. Keep your SOIC's and SOT's
perpendicular to the wave (long part of the body with pins parallel to the
wave so each side of pins solder at same time). Chip components 603,805,1206
normally do not cause too many problems unless they are too close. Also
keep larger parts away from smaller parts to prevent shadowing in wave.
For Pad sizes on SOT's, I have had excellent results with 0.035"w x 0.055"l
with 0.090" separation from single pad to dual, with a 0.0375" separation
between dual pads.
For SOIC's Narrows, 0.028"w x 0.094"l on 0.050" lead pitch.
For SOIC's Wide, 0.028"w x .102"l on 0.050" lead pitch.
Hope this may help a little!
Tom Braswell
Fawn Industries
6441 East NC 97
Elm City, NC 27822
Ph: (252) 977-8745
Fx: (252) 977-3477
Email: [log in to unmask]
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Kelly Morris
> Sent: Thursday, May 24, 2001 4:33 PM
> To: [log in to unmask]
> Subject: [TN] SOT23 opens & DOE Test board layout.
>
>
> Hi All:
> This is my first time on Technet,,,so be gentle with me.
>
> We’ve got a problem here with opens on bottom side wave soldered SOT23s.
> Based on past experience and review of the fine Technet archives, I feel
> that our main problem is pad size. We have the same size pads for bottom
> side SOT23s as we have for the top (which is .035” by .035” with .080”
> between the single pad center to the double pad center).
>
> I’m going to design a test board that we can use in running a DOE to see
> what would be the optimal pad size to reduce/eliminate opens on these
> components, but not consume any more real estate than necessary.
>
> While I’m at it I’m going to play with pad sizes for 0402s up
> thru 1206s as
> well as some different SOICs.
> Since we have a standard pallet size here, I’ve got all kinds of real
> estate (8.3” x 11.25”)
>
> I was wondering if anyone out there, who has been through this
> before would
> have any advice on things to be concerned with while laying out this test
> board.
>
>
> TIA;
>
> Kelly
>
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