Kelly,

When you say opens do you really mean "solder skips"?


Martin Christie


-----Original Message-----
From: Kelly Morris [mailto:[log in to unmask]]
Sent: 24 May 2001 21:33
To: [log in to unmask]
Subject: [TN] SOT23 opens & DOE Test board layout.


Hi All:
This is my first time on Technet,,,so be gentle with me.

We've got a problem here with opens on bottom side wave soldered SOT23s.
Based on past experience and review of the fine Technet archives, I feel
that our main problem is pad size.  We have the same size pads for bottom
side SOT23s as we have for the top (which is .035" by .035" with .080"
between the single pad center to the double pad center).

I'm going to design a test board that we can use in running a DOE to see
what would be the optimal pad size to reduce/eliminate opens on these
components, but not consume any more real estate than necessary.

While I'm at it I'm going to play with pad sizes for 0402s up thru 1206s as
well as some different SOICs.
Since we have a standard pallet size here, I've got all kinds of real
estate (8.3" x 11.25")

I was wondering if anyone out there, who has been through this before would
have any advice on things to be concerned with while laying out this test
board.


TIA;

Kelly

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