One possible solution would be to change your test probes from a chisel type
to one with multiple points, resembling a king's crown.

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>


        -----Original Message-----
        From:   Dan Ratcliff 727-530-8762 [SMTP:[log in to unmask]]
        Sent:   Thursday, May 17, 2001 3:53 PM
        To:     [log in to unmask]
        Subject:        [TN] ICT after double sided reflow

        Hey all,

        We have a multilayer .062 thk blind/buried/thru via OSP PCB designed
as
        a double sided reflow assembly.  The assembly process went fine
until
        the boards reached ICT.  The board has .030 dia. testpoints with and
        without .010 dia. holes.  Prior to this we used .040 dia test pads
with
        .010 holes which after researching the issue, we felt could be
reduced
        to .030.  These testpoints function as ICT probe sites and as
circuit
        interconnect vias.  When we tested the first PCB's we found that
because
        the testpoints were not soldered the OSP was not removed from the
test
        pads.   As a result, the test probes (high force chisel probes) did
not
        reliably penetrate through the residual OSP to make contact with the
        test land.  For our second attempt, we applied a 1X paste print to
the
        testpoints prior to reflow.  The result was that while we got a good
        surface for the probe to contact, some solder and flux residue ended
up
        in the holes and the test probes did not reliably penetrate the flux
        residue.  For the third attempt, we overprinted the paste (.040) on
the
        testpoints in an attempt to create enough solder volume to fill the
hole
        and create a relatively flat surface to probe without the hole
capturing
        flux residue.  Unfortunately due to the proximity of adjacent
features
        there were some testpoints which could not be overprinted.  This
        resulted in improved ICT yields but still left failures.  The fourth
        modification was to build a new ICT fixture which had tighter
        tolerances, enhanced probe types and an alignment plate.  This step
        addressed the difficulty of hitting the .030 test pads reliably and
        produced very good results.  Finally we changed the paste chemistry
by
        using a differant solderpaste.  This seemed to eliminate the
remaining
        solder issues because the paste has a higher metal content an the
        residual flux did not prevent the probes from making contact with
the
        test pads.  The production engineers drew the conclusion from all of
        this that we can not reliably hit a .030 diameter test pad and that
all
        double sided reflow designs must have testpoints without holes in
them.
        This was OK when we had a microvia design.  However, going forward
we
        are looking at very dense double sided reflow .093 thk OSP PCB's
with
        thru vias only.  We lack the real estate to have a via and test land
at
        separate locations in densely populated analog areas.  I would like
to
        hear how other folks are dealing with double sided reflow and ICT.
Is
        it really necessary to avoid holes in the test lands?  Is it
possible to
        have reliable ICT test with .040 dia. probe sites and .010 dia.
holes in
        them?

        Thx in advance for your help,
        Dan Ratcliff
        Sr. PCB Designer
        Paradyne Corporation, Largo FL
        727-530-8762


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