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Thu, 24 May 2001 18:09:25 -0700 |
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Guy,
You may want to make sure that the more overhanging lead is not now able
to rest directly over an adjacent trace. With this smaller SMD land may
need larger trace design keepouts around the SMD lands to avoid potential
lead over trace reliability issue.
| _____
| /____ /\ Karl Sauter, Staff Engineer
| /____ \\ \ Sun Microsystems, Inc., M/S: MPK15-103
| /_____\ \\ / VLSI/Advanced Component Engineering
| /_____/ \/ / / 901 San Antonio Road
| /_____/ / \//\ Palo Alto, CA 94303
| \_____\//\ / /
| \_____/ / /\ / Phone: 650-786-7663
| \_____/ \\ \ Email: [log in to unmask]
| \_____\ \\
| \_____\/
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> Date: Thu, 24 May 2001 20:22:33 EDT
> From: Werner Engelmaier <[log in to unmask]>
> Subject: Re: [TN] IPC land to lead fillet requirements
> X-To: [log in to unmask]
> To: [log in to unmask]
>
> Hi Guy,
> There is no reliability down side; in fact Class 3 is overkill on this
> issue. Tests have shown no reliability impact until offset exceeds 60%
> [that is 40% lead on land]. Thus, Class 2 is perfectly o.k. on this
> issue. The reference is in IPC-D-279.
>
> Werner Engelmaier
> Engelmaier Associates, L.C.
> Electronic Packaging, Interconnection and Reliability Consulting
> 7 Jasmine Run
> Ormond Beach, FL 32174 USA
> Phone: 904-437-8747, Fax: 904-437-8737
> E-mail: [log in to unmask], Website: www.engelmaier.com
>
>
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Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
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