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April 2001

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Subject:
From:
"<Peter George Duncan>" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 25 Apr 2001 12:32:14 +0800
Content-Type:
text/plain
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text/plain (100 lines)
Hi, Patrick,

As you've probably gathered by now, TechNet doesn't accept attachments, so
I cannot look at your table. I'm also no active PCB designer, only a
passive one, looking over the shoulders of others. However, population
density of a board depends on a number of factors that include:

   Board material and dielectric thickness
   Power running through the board
   Signal separation requirements
   In circuit testing (this takes up a lot of real estate on a board since
   you have to have a test pad for every net plus pull-up or pull-down
   resistors to isolate IC's for testing plus a minimum pad size and
   spacing to permit access to the test pads by the test jig probes). If
   you can carry out simulator testing using a Test Access Connector or the
   I/O connectors instead of ICT, then I recommend that for space saving.
   Many people like to use Leadless Chip Carriers or BGA's, etc., as a
   means of saving space on a card - you don't have all those leads
   sticking out and taking up space. You should, though, be aware of the
   Co-efficient of Thermal Expansion (CTE) differences between these
   components and the board material and the problems this causes, should
   you choose to go down that route.
   Avoid having too much tracking on the outer layers. There is a
   compromise to be reached between surface tracking, the number of via
   holes and the number of layers you need to have, but surface tracking
   also takes up a lot of space.
   If you're building conduction-cooled boards, you may have large lock-out
   (aka keep-out) areas on the card surface for heatsinks/conductors and
   thermal via hole features that limit tracking area and component
   placement positons.

Hope this helps a bit. There are plenty of PCB gurus on TN who can give you
more detail.

Pete Duncan




                    "Lam, Patrick"
                    <Patrick.Lam@GLE        To:     [log in to unmask]
                    NAYRE.COM>              cc:
                    Sent by: TechNet        Subject:     [TN] Minimum Spacing For SMD
                    <[log in to unmask]
                    >


                    04/25/01 12:25
                    AM
                    Please respond
                    to "TechNet
                    E-Mail Forum.";
                    Please respond
                    to "Lam,
                    Patrick"






Hi all,

We need to pack all the components as close to each other as possible onto
both sides of the board. Please share your knowledge on how to determine
the
minimum spacing for a manufacturable design. Please give feed back to the
spacings(attached table in inches)we are using. Please tell me which ones
can go tighter?!

Thanks,

Patrick Lam
Phone:(604)293.4392

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