RF Assembly Issues:
Marty...
I've been following the messages on your RF Problems...
While I don't disagree with anything I have read so far, I would certainly
attempt to
first eliminate two simple variables from your equation,... solder paste and
reflow profile. both of these can GREATLY contribute to your success or
failure.
You stated in earlier messages that you a) removed and replaced your
transceiver chip, but unless I've missed it, I am unclear on what the result
of this was, please clarify b) by replacing the transceiver with a new
one, you indicated that performance was much better.
At your frequency, (sub 1GHZ), I'm surprised to hear of your difficulties.
I agree with the others that component selection, or board design, can in
fact be the underlying issue, but wouldn't start dissecting it until you
have eliminated the simpler variables.
When you re-work the device, what piece of equipment do you use and what
type of thermal cycle or profile do you use.
When you remove and replace the device, are you using any extra or
alternative flux or paste to re-attach it.
Have you tried simply re-heating or re-reflowing the device without removing
it, and without the addition of any flux. If not, try re-heating the device
to about 170 C for somewhere between 1 to 2 minutes and then retest after it
cools down. If that doesn't work, try re-reflowing the device, taking care
to monitor your thermal cycle.
Let us know if any of this helps, hurts, or is redundant
regards
Jim Wertin
Technical Applications Manager
AIM, Inc.
[log in to unmask]
----- Original Message -----
From: "Automatic digest processor" <[log in to unmask]>
To: "Recipients of TechNet digests" <[log in to unmask]>
Sent: Friday, March 30, 2001 12:10 PM
Subject: TechNet Digest - 29 Mar 2001 to 30 Mar 2001 - Special issue
(#2001-193)
> There are 9 messages totalling 945 lines in this issue.
>
> Topics in this special issue:
>
> 1. Collasped Height of BGAs/CSPs
> 2. BGA crack Summary, theory, and questions (4)
> 3. Lacing Tape (2)
> 4. Graph for PCB Laminate Usage
> 5. RF Assembly Issues
>
> --------------------------------------------------------------------------
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> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> --------------------------------------------------------------------------
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>
> ----------------------------------------------------------------------
>
> Date: Fri, 30 Mar 2001 08:55:30 +0200
> From: "Ingemar Hernefjord (EMW)" <[log in to unmask]>
> Subject: Re: Collasped Height of BGAs/CSPs
>
> Depends on weight, Hann.
> The heavier the package, the more compressed balls. If you talk collapsed
balls. I have had a look on BGAs from some 200 up to 1200 balls, and with
varying weight. They seem to collapse so that you get a delta from anything
between 10% height reduction to 50%. The later are called 'squashy' by guru
W. Notice that the delta can be both plus or minus! All balls are not
necessarily compressed. If we have to do with a 'manta' package, the bowing
can cause both elongated and compressed shapes. IBM Fishkill once put into
my head that the resulting balls must have a barrel form, but I now learn
that the shape is not so essential in most practical applications. But of
cause the computer is right in theory.
> Ingemar
>
> -----Original Message-----
> From: Hann Pang [mailto:[log in to unmask]]
> Sent: den 29 mars 2001 18:53
> To: [log in to unmask]
> Subject: [TN] Collasped Height of BGAs/CSPs
>
>
> HI Technet experts,
>
> 1) Can someone tell me what kind of heights i can expect between a 12mm
> x 12mm full area array BGA package and the substrate after reflow.?
>
> 2) How do they typically differ for Packages of different sizes,
arrays,
> I/O counts and solder balls?
>
>
>
> Thanks in advance!
>
> Hann
>
> 3M
>
> --------------------------------------------------------------------------
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> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following message: SET
Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>
> ------------------------------
>
> Date: Fri, 30 Mar 2001 07:30:58 -0600
> From: David Hillman <[log in to unmask]>
> Subject: Re: BGA crack Summary, theory, and questions
>
> Hi Rudolph! Some comments:
>
> "I hope this is not too much for you guys. I just wish that one day I can
> find out the root cause for this interesting case ( for me at least).
> There
> are so many responses since I sent out my question yesterday. Because of
> my
> workload, I am sorry that I cannot reply and thanks each of you."
>
> ** Don't worry about having a problem that seems huge. Technet can solve
> both easy and impossible problems - it just takes the group three days
> longer to solve the impossible stuff!
>
> "Now to my theory and please don't laugh if it sounds funny."
>
> ** There is never a silly question (well maybe except for a few from Doug
> Pauls before he has his morning caffeine)
>
> "Can a current high enough to generate heat to the joint and thicken the
> intermetallic layer or simply induce a crack to the joint? The failure
> joint is used as an bi-polar address line which requires a very small amp.
> But what if a nearby circuitry, which carry a strong current, shorts with
> the trace attached to the ball because of low yield from the fab vendor (A
> build-in narrow electrical spacing ) Can the intermetallic layer /joint
be
> affected by this?"
>
> ** Interesting theory. I have not seen a case nor could I find a case of
> excess current in a trace inducing sufficient intermetallic growth to
cause
> a solder joint failure. There have been a couple of cases of overheating
to
> a point of melting the solder joint which resulted in failure.
>
> "Question:
> What is the intermetallic growth rate with Tin/lead and Ni?"
>
> ** Take a look at page 101 of the American Welding Society's Soldering
> Handbook, 3rd Edition, Editor Paul Vianco, ISBN 0-87171-618-6. The growth
> rate of SnNi intermetallic at 170C (338F) was approximately 6 um (157
> uinches) over a 4 day period. That would be a lot of intermetallic but I
> would have trouble believing that you could have a trace sustain a 170C
> temperature for a 4 day period of time. Therefore the amount of
> intermetallic you would generate over a short period of time at an
elevated
> temperature would most likely not result in significant growth of the
> intermetallic.
>
> Hope this helps. Good Luck.
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
>
>
>
> Rudolph Yu <[log in to unmask]>@IPC.ORG> on 03/29/2001 05:02:06 PM
>
> Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please
respond
> to Rudolph Yu <[log in to unmask]>
>
> Sent by: TechNet <[log in to unmask]>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: [TN] BGA crack Summary, theory, and questions
>
>
> I hope this is not too much for you guys. I just wish that one day I can
> find out the root cause for this interesting case ( for me at least).
> There
> are so many responses since I sent out my question yesterday. Because of
> my
> workload, I am sorry that I cannot reply and thanks each of you.
>
> Let me just quickly summarize my problem, and I want to share with the
> group
> one of my theories of how this could happen. Since I don't have a EE
> degree, so it may sounds funny to many of you. I want to know if this make
> sense at all to you guys.
>
> Problem: BGA Mirco -fracture was found on every 4-5K boards we built at a
> same I/O. The board is a single sided with through hole connectors.
> (reflow
> and wave) (actually we also had used the paste in hole process and see the
> same failure mode).The board is FR4, 8layers with HASL finish. The same
> ASIC is used on the other product with no failure reported. ( yes, the
vias
> routing on the fab is different between the two design)
> If you are interested in this case, Stephen R. Gregory had helped me to
> post
> my pictures at http:www.xdrive.com/share/985835366039IhSi4tEHHweAj9vYGZA6
>
> George, Robert and several of you have pointed out the double reflow
> phenomenon, and that the pad with a long trace to the via can induce
stress
> to the joint. A very good point.
> However I just find out that our oversea contractor did also use the
> paste-in-hole process as part of the experiment, ( As you see, i just
> picked
> up the project) and some of those boards have the same problem too.
>
> Now my first question of the day: If double reflow on the SMT joint is
> indeed the root cause for the failure at this particular joint, should it
> happens more frequently than 1 out of every 4-5 thousand boards we built?
> How repeatable this phenomenon should be?
>
> Now to my theory and please don't laugh if it sounds funny.
>
> Can a current high enough to generate heat to the joint and thicken the
> intermetallic layer or simply induce a crack to the joint? The failure
> joint is used as an bi-polar address line which requires a very small amp.
> But what if a nearby circuitry, which carry a strong current, shorts with
> the trace attached to the ball because of low yield from the fab vendor (A
> build-in narrow electrical spacing ) Can the intermetallic layer /joint
be
> affected by this?
>
> Question:
>
> What is the intermetallic growth rate with Tin/lead and Ni?
> How much current does it needs to have to increase 1 degree C at the
joint?
>
> I am going to the CAD group to see if the trace spacing had been violated
> or
> is abnormal on this product.
>
>
> Comments, thought, or it is enough??
>
> Anyway, thanks for taking the time reading this.
>
> Rudolph Yu
>
> --------------------------------------------------------------------------
-------
>
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following message: SET
> Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
-------
>
> ------------------------------
>
> Date: Fri, 30 Mar 2001 08:46:11 -0500
> From: Bev Christian <[log in to unmask]>
> Subject: Re: BGA crack Summary, theory, and questions
>
> Dave,
> A little birdy tells me that you are taking possession of your Jewelbox 90
> shortly. How are things going?
>
> Bev
>
> -----Original Message-----
> From: David Hillman [mailto:[log in to unmask]]
> Sent: March 30, 2001 8:31 AM
> To: [log in to unmask]
> Subject: Re: [TN] BGA crack Summary, theory, and questions
>
>
> Hi Rudolph! Some comments:
>
> "I hope this is not too much for you guys. I just wish that one day I can
> find out the root cause for this interesting case ( for me at least).
> There
> are so many responses since I sent out my question yesterday. Because of
> my
> workload, I am sorry that I cannot reply and thanks each of you."
>
> ** Don't worry about having a problem that seems huge. Technet can solve
> both easy and impossible problems - it just takes the group three days
> longer to solve the impossible stuff!
>
> "Now to my theory and please don't laugh if it sounds funny."
>
> ** There is never a silly question (well maybe except for a few from Doug
> Pauls before he has his morning caffeine)
>
> "Can a current high enough to generate heat to the joint and thicken the
> intermetallic layer or simply induce a crack to the joint? The failure
> joint is used as an bi-polar address line which requires a very small amp.
> But what if a nearby circuitry, which carry a strong current, shorts with
> the trace attached to the ball because of low yield from the fab vendor (A
> build-in narrow electrical spacing ) Can the intermetallic layer /joint
be
> affected by this?"
>
> ** Interesting theory. I have not seen a case nor could I find a case of
> excess current in a trace inducing sufficient intermetallic growth to
cause
> a solder joint failure. There have been a couple of cases of overheating
to
> a point of melting the solder joint which resulted in failure.
>
> "Question:
> What is the intermetallic growth rate with Tin/lead and Ni?"
>
> ** Take a look at page 101 of the American Welding Society's Soldering
> Handbook, 3rd Edition, Editor Paul Vianco, ISBN 0-87171-618-6. The growth
> rate of SnNi intermetallic at 170C (338F) was approximately 6 um (157
> uinches) over a 4 day period. That would be a lot of intermetallic but I
> would have trouble believing that you could have a trace sustain a 170C
> temperature for a 4 day period of time. Therefore the amount of
> intermetallic you would generate over a short period of time at an
elevated
> temperature would most likely not result in significant growth of the
> intermetallic.
>
> Hope this helps. Good Luck.
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
>
>
>
> Rudolph Yu <[log in to unmask]>@IPC.ORG> on 03/29/2001 05:02:06 PM
>
> Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please
respond
> to Rudolph Yu <[log in to unmask]>
>
> Sent by: TechNet <[log in to unmask]>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: [TN] BGA crack Summary, theory, and questions
>
>
> I hope this is not too much for you guys. I just wish that one day I can
> find out the root cause for this interesting case ( for me at least).
> There
> are so many responses since I sent out my question yesterday. Because of
> my
> workload, I am sorry that I cannot reply and thanks each of you.
>
> Let me just quickly summarize my problem, and I want to share with the
> group
> one of my theories of how this could happen. Since I don't have a EE
> degree, so it may sounds funny to many of you. I want to know if this make
> sense at all to you guys.
>
> Problem: BGA Mirco -fracture was found on every 4-5K boards we built at a
> same I/O. The board is a single sided with through hole connectors.
> (reflow
> and wave) (actually we also had used the paste in hole process and see the
> same failure mode).The board is FR4, 8layers with HASL finish. The same
> ASIC is used on the other product with no failure reported. ( yes, the
vias
> routing on the fab is different between the two design)
> If you are interested in this case, Stephen R. Gregory had helped me to
> post
> my pictures at http:www.xdrive.com/share/985835366039IhSi4tEHHweAj9vYGZA6
>
> George, Robert and several of you have pointed out the double reflow
> phenomenon, and that the pad with a long trace to the via can induce
stress
> to the joint. A very good point.
> However I just find out that our oversea contractor did also use the
> paste-in-hole process as part of the experiment, ( As you see, i just
> picked
> up the project) and some of those boards have the same problem too.
>
> Now my first question of the day: If double reflow on the SMT joint is
> indeed the root cause for the failure at this particular joint, should it
> happens more frequently than 1 out of every 4-5 thousand boards we built?
> How repeatable this phenomenon should be?
>
> Now to my theory and please don't laugh if it sounds funny.
>
> Can a current high enough to generate heat to the joint and thicken the
> intermetallic layer or simply induce a crack to the joint? The failure
> joint is used as an bi-polar address line which requires a very small amp.
> But what if a nearby circuitry, which carry a strong current, shorts with
> the trace attached to the ball because of low yield from the fab vendor (A
> build-in narrow electrical spacing ) Can the intermetallic layer /joint
be
> affected by this?
>
> Question:
>
> What is the intermetallic growth rate with Tin/lead and Ni?
> How much current does it needs to have to increase 1 degree C at the
joint?
>
> I am going to the CAD group to see if the trace spacing had been violated
> or
> is abnormal on this product.
>
>
> Comments, thought, or it is enough??
>
> Anyway, thanks for taking the time reading this.
>
> Rudolph Yu
>
> --------------------------------------------------------------------------
--
> -----
>
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following message: SET
> Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
--
> -----
>
> --------------------------------------------------------------------------
--
> -----
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following message: SET
> Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
--
> -----
>
> ------------------------------
>
> Date: Fri, 30 Mar 2001 08:37:44 -0500
> From: Lou Hart <[log in to unmask]>
> Subject: Re: BGA crack Summary, theory, and questions
>
> Rudolph, I can't advise you or anyone on issues of double reflow,
> intermetallic growth, etc, but I would suggest if you are not already
> familiar with Poisson statistics that you become so, or get some guidance
> on such matters. If 1/5000 are failing and you implement a proposed
> solution, figure out in advance how long you will have to observe the new
> product to prove to everyone's satisfaction that the fix works. Lou Hart
>
> -----Original Message-----
> From: Rudolph Yu [SMTP:[log in to unmask]]
> Sent: Thursday, March 29, 2001 6:02 PM
> To: [log in to unmask]
> Subject: [TN] BGA crack Summary, theory, and questions
>
> I hope this is not too much for you guys. I just wish that one day I can
> find out the root cause for this interesting case ( for me at least).
> There
> are so many responses since I sent out my question yesterday. Because of
> my
> workload, I am sorry that I cannot reply and thanks each of you.
>
> Let me just quickly summarize my problem, and I want to share with the
> group
> one of my theories of how this could happen. Since I don't have a EE
> degree, so it may sounds funny to many of you. I want to know if this make
> sense at all to you guys.
>
> Problem: BGA Mirco -fracture was found on every 4-5K boards we built at a
> same I/O. The board is a single sided with through hole connectors.
> (reflow
> and wave) (actually we also had used the paste in hole process and see the
> same failure mode).The board is FR4, 8layers with HASL finish. The same
> ASIC is used on the other product with no failure reported. ( yes, the
vias
> routing on the fab is different between the two design)
> If you are interested in this case, Stephen R. Gregory had helped me to
> post
> my pictures at http:www.xdrive.com/share/985835366039IhSi4tEHHweAj9vYGZA6
>
> George, Robert and several of you have pointed out the double reflow
> phenomenon, and that the pad with a long trace to the via can induce
stress
> to the joint. A very good point.
> However I just find out that our oversea contractor did also use the
> paste-in-hole process as part of the experiment, ( As you see, i just
> picked
> up the project) and some of those boards have the same problem too.
>
> Now my first question of the day: If double reflow on the SMT joint is
> indeed the root cause for the failure at this particular joint, should it
> happens more frequently than 1 out of every 4-5 thousand boards we built?
> How repeatable this phenomenon should be?
>
> Now to my theory and please don't laugh if it sounds funny.
>
> Can a current high enough to generate heat to the joint and thicken the
> intermetallic layer or simply induce a crack to the joint? The failure
> joint is used as an bi-polar address line which requires a very small amp.
> But what if a nearby circuitry, which carry a strong current, shorts with
> the trace attached to the ball because of low yield from the fab vendor (A
> build-in narrow electrical spacing ) Can the intermetallic layer /joint
be
> affected by this?
>
> Question:
>
> What is the intermetallic growth rate with Tin/lead and Ni?
> How much current does it needs to have to increase 1 degree C at the
joint?
>
> I am going to the CAD group to see if the trace spacing had been violated
> or
> is abnormal on this product.
>
>
> Comments, thought, or it is enough??
>
> Anyway, thanks for taking the time reading this.
>
> Rudolph Yu
>
> ------------------------------
>
> Date: Fri, 30 Mar 2001 08:51:59 -0500
> From: Bev Christian <[log in to unmask]>
> Subject: Re: BGA crack Summary, theory, and questions
>
> Opps! The finger key was quicker than the old noodle. Sorry.
>
> ------------------------------
>
> Date: Fri, 30 Mar 2001 09:29:37 -0500
> From: bbarr <[log in to unmask]>
> Subject: Lacing Tape
>
> Not exactly a high-tech question, but...could anybody point me to a
> document, web site, etc. that shows the proper method for tying lacing
cord
> knots? Our customer wants us to tie down socketed ICs with lacing cord. I
> have been away from defense work too long to remember where this info came
> from.
>
> Thanks.
>
>
> Bob
>
>
> Robert Barr
> Manufacturing Engineering
> Formation, Inc.
> Voice: 856-234-5020 x3035
> Fax: 856-234-6679
> email: [log in to unmask]
>
> ------------------------------
>
> Date: Fri, 30 Mar 2001 17:42:13 +0200
> From: Roland Jaquet <[log in to unmask]>
> Subject: Re: Graph for PCB Laminate Usage
>
> C'est un message de format MIME en plusieurs parties.
>
> ------=_NextPart_000_0030_01C0B940.C0EB3760
> Content-Type: text/plain;
> charset="iso-8859-1"
> Content-Transfer-Encoding: quoted-printable
>
> Hi Harold,
>
> I do not have this info, but I have most manufacturers and contacts on =
> my webpage under Laminates, if it can help you.
>
> Very Best Regards
>
> Roland
>
> Http://www.PCBspecialist.com
> Roland Jaquet - PCBspecialist - 21 Grand-Voiret - CH-1228 =
> Plan-Les-Ouates - Geneva - Switzerland - Tel. +41-22-880-0405 - GSM =
> (cellphone) +41-79-203-3723 - Fax +41-22-880-0409 - Company Viability - =
> Technical Viability - Technology Choice - Yield Improvement - Company =
> Strategy - Equipment Choice - Company Acquisition
> ----- Message d'origine -----=20
> De : Harold G. Bailey=20
> =C0 : [log in to unmask]
> Envoy=E9 : mercredi, 28. mars 2001 18:15
> Objet : [TN] Graph for PCB Laminate Usage
>
>
> Can anyone provide me with a graph showing the square footage of
> the different types of laminate use in the industry for 2001 or =
> projected
> use in 2002.
>
> =
> -------------------------------------------------------------------------=
> --------
> Technet Mail List provided as a free service by IPC using LISTSERV =
> 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text =
> in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following message: =
> SET Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line Resources & =
> Databases > E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
> additional
> information, or contact Keach Sasamori at [log in to unmask] or =
> 847-509-9700 ext.5315
> =
> -------------------------------------------------------------------------=
> --------
>
> ------=_NextPart_000_0030_01C0B940.C0EB3760
> Content-Type: text/html;
> charset="iso-8859-1"
> Content-Transfer-Encoding: quoted-printable
>
> <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
> <HTML><HEAD>
> <META http-equiv=3DContent-Type content=3D"text/html; =
> charset=3Diso-8859-1">
> <META content=3D"MSHTML 5.50.4611.1300" name=3DGENERATOR>
> <STYLE></STYLE>
> </HEAD>
> <BODY bgColor=3D#ffffff>
> <DIV><FONT face=3DArial size=3D2>Hi Harold,</FONT></DIV>
> <DIV><FONT face=3DArial size=3D2></FONT> </DIV>
> <DIV><FONT face=3DArial size=3D2>I do not have this info, but I have =
> most=20
> manufacturers and contacts on my webpage under Laminates, if it can help =
>
> you.</FONT></DIV>
> <DIV><FONT face=3DArial size=3D2></FONT> </DIV>
> <DIV>Very Best Regards</DIV>
> <DIV> </DIV>
> <DIV>Roland</DIV>
> <DIV> </DIV>
> <DIV><A=20
> href=3D"http://www.PCBspecialist.com">Http://www.PCBspecialist.com</A><BR=
> >Roland=20
> Jaquet - PCBspecialist - 21 Grand-Voiret - CH-1228 Plan-Les-Ouates - =
> Geneva -=20
> Switzerland - Tel. +41-22-880-0405 - GSM (cellphone) +41-79-203-3723 - =
> Fax=20
> +41-22-880-0409 - Company Viability - Technical Viability - Technology =
> Choice -=20
> Yield Improvement - Company Strategy - Equipment Choice - Company=20
> Acquisition</DIV>
> <BLOCKQUOTE=20
> style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
> BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
> <DIV style=3D"FONT: 10pt arial">----- Message d'origine ----- </DIV>
> <DIV style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
> black"><B>De=20
> :</B> <A [log in to unmask]
> href=3D"mailto:[log in to unmask]">Harold G. Bailey</A> =
> </DIV>
> <DIV style=3D"FONT: 10pt arial"><B>=C0 :</B> <A =
> [log in to unmask]
> href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
> <DIV style=3D"FONT: 10pt arial"><B>Envoy=E9 :</B> mercredi, 28. =
> mars 2001=20
> 18:15</DIV>
> <DIV style=3D"FONT: 10pt arial"><B>Objet :</B> [TN] Graph for PCB =
> Laminate=20
> Usage</DIV>
> <DIV><BR></DIV>Can anyone provide me with a graph showing the square =
> footage=20
> of<BR>the different types of laminate use in the industry for 2001 or=20
> projected<BR>use in=20
> =
> 2002.<BR><BR>------------------------------------------------------------=
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> --------------------</BLOCKQUOTE></BODY></HTML>
>
> ------=_NextPart_000_0030_01C0B940.C0EB3760--
>
> ------------------------------
>
> Date: Fri, 30 Mar 2001 08:00:19 -0800
> From: Phil Crepeau <[log in to unmask]>
> Subject: Re: RF Assembly Issues
>
> hi,
>
> as was mentioned, rf designs and designers are weird. their weirdness is
only outdone by antenna designs and designers. theirs is not a
'plug-and-play' world, so tweaking may be inevitable.
>
> phil
>
> -----Original Message-----
> From: Marty Brooks [mailto:[log in to unmask]]
> Sent: Thursday, March 29, 2001 3:12 PM
> To: [log in to unmask]
> Subject: Re: [TN] RF Assembly Issues
>
>
> Thanks everyone for your input.
>
> To respond to some of the comments:
>
> Phil - Yes, we removed the chip and resoldered the same chip to the pwb.
> Problem is How can I tell the vendor to perform a labour intensive rework
> procedure in a mass production environment without the vendor charging me
> for it. I will argue their process is causing the problem, they will
argue
> it's our design. And yes, we did replace the poorly performing part with
a
> 'new' one and performance was much better with the new part. This all
leads
> me down the path of solder joint quality - I just need some way to prove
> that to the vendor.
>
> Steve - I think the bottom only terminations of the chip does pose a
> problem. Have other assembly shops had problems with devices like this
and
> how have they overcome them? The chip is a ceramic base with gold plated
> terminations.
>
> Dave - I've considered the trace dimensions. They are all optimized as
best
> they can, except for the Xceiver chip which has pads 10mil longer than
> recommended by the manufacturer. I wonder if that extra length, as small
as
> it is, would be enough to throw the impedance out of whack? Something
that
> I will look into.
>
> Ingemar/James - I'm no RF engineer either. The device operates at 900MHz.
> Board is FR4 with a dielectric constant of 4.1 or 4.2. Board is impedance
> controlled to 50ohms. Surrounding components are 0603 resistors and
caps -
> except for the RF output line which goes through a 15nH wire wrapped
> inductor. We have optimized the layout and moved all the components as
> close together as possible to minimize any transmission line anomalies
that
> may want to appear. As far as your other questions, naturally I don't
have
> those at my fingertips, but I'll see what I can dig up and present them to
> the first RF guru I can track down.
>
> You have provided some new points for consideration though.
>
> Thanks
> Marty
>
>
> -----Original Message-----
> From: Ingemar Hernefjord (EMW)
> [mailto:[log in to unmask]]
> Sent: Thursday, March 29, 2001 6:51 AM
> To: [log in to unmask]
> Subject: Re: [TN] RF Assembly Issues
>
>
> Marty, sounds like you have to use a fishbone modelling. So many
parameters
> that could have impact. You don't say what kind of part you are making,
> something for under 2GHz or much above? And nothing about dielectric and
> surrounding components, ground planes, distriubution kind of traces, noise
> level requirements, spurioses, I/O-loading etc. Not easy for an RF
engineer
> to give advice. Have you modelled the circuit and simulated variations in
a
> computer? If you are talking very high frequencies, even length of
bondwires
> on inside of package plays a role. And what's the package made of, ceramic
> or plastic? If you ask an RFspecialist to engage you need prepare to give
> information about:
>
> epsilon as function of temperature for your board material, as well as for
> all the components
> RF-parameters (S e.g.)as function of temperature
> possible hysteresis of your ceramic caps, if you use such (behave
different
> on way up and down T)
> identification of the parameter that gives your freq shift (Temp sensitive
> part on inside of 20leg)
> checking if you really use valid test set up (microwave is tricky)
> checking possible ferroelectric phenomenons in ceramic components, if you
> use such
> what kind of tuning components do you use? Are they temperature sensitive?
> As James said, check all return paths, also crosstalking and feedback
> traces.
> and many more questions, depending on the complexity of your circuit
> diffusion phenomenons that can change chip data
> Tin, Silver migration that can cause bridging
>
>
> I recommend you to see nearest RF engineer in person. RF problems are
rarely
> solved by mail. If it is a RF-problem at all! Try not to solder the 20pin
at
> all. Mount some 10 boards using silverepoxy mounting the 20pin after first
> soldering all other components. Aftermounting with other words. If all 10
> get center freq where it should be, then the 20pin could be temp
sensitive.
>
> In fact your questions seems to reveal that you are not making an advanced
> HF circuit but something for the commercial 'low freq' market, a radio
board
> or so. Important for you to tell TN, because the 'RF' guys are either
> ordinary and sound radio/TV/equipment makers..or Telecom/MIL/SPACE 'real'
RF
> neurds with doctor's grade and at least 500 empty Coca bottles on the
> wall..2GHZ is called DC among the later...
>
> Ingemar
>
> -----Original Message-----
> From: Marsico, James [mailto:[log in to unmask]]
> Sent: den 29 mars 2001 14:50
> To: [log in to unmask]
> Subject: Re: [TN] RF Assembly Issues
>
>
> Most of the time, RF components need the body (under the component)
soldered
> to the PWB for proper grounding. I'm no RF engineer, (God forbid) but I
> understand that this grounding can be critical for performance. Perhaps
> this is a good place to start.
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> AIL/Electronics Systems Group
> An EDO Company
> [log in to unmask] <mailto:[log in to unmask]>
>
> -----Original Message-----
> From: Marty Brooks [SMTP:[log in to unmask]]
> Sent: Wednesday, March 28, 2001 4:41 PM
> To: [log in to unmask]
> Subject: [TN] RF Assembly Issues
>
> We are experiencing a concerning variation from board to board in
> the
> performance of our RF product. We have investigated several
causes
> of the
> problem and are currently of the opinion that soldering quality of
> the
> transceiver chip is the most significant contributing factor. As
an
> example, on the last run of prototypes that was manufactured, the
> signal
> frequency was at the upper limit of the allowable range. We
removed
> and
> replaced the transceiver chip in-house and decreased the frequency
> closer to
> what we would expect.
>
> I'm going to be making a visit to our contractor's facility next
> week to
> investigate this problem and would like some feedback on possible
> causes or
> process controls that I should look into.
>
> The board is 4 layers, HASL finish, single side smt, solder paste
> used is
> Alpha's UP78 no-clean. The transceiver chip is a 20-pin device
with
> terminations flush along the bottom of the component.
>
> Thanks for any advice.
>
> Marty Brooks
> Manufacturing Engineer
> IDENTEC Solutions, Inc.
> 102, 1860 Dayton Street
> Kelowna, B.C., Canada V1Y 7W6
> Ph:(250)860-6567, Fax:(250)860-6541
> www.identec.com
>
> This email contains confidential information and is intended for
the
> sole
> use of the addressee. Any other distribution, copying or
disclosure
> is
> strictly prohibited. If you are not the addressee, please notify
the
> sender
> by email and delete this message.
>
>
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> ------------------------------
>
> Date: Fri, 30 Mar 2001 11:19:36 -0500
> From: "Terveen, James @ NARDAEAST" <[log in to unmask]>
> Subject: Re: Lacing Tape
>
> try this sight
>
> http://ourworld.compuserve.com/homepages/g_knott/elect23.htm
>
> -----Original Message-----
> From: bbarr [mailto:[log in to unmask]]
> Sent: Friday, March 30, 2001 9:30 AM
> To: [log in to unmask]
> Subject: [TN] Lacing Tape
>
>
> Not exactly a high-tech question, but...could anybody point me to a
> document, web site, etc. that shows the proper method for tying lacing
cord
> knots? Our customer wants us to tie down socketed ICs with lacing cord. I
> have been away from defense work too long to remember where this info came
> from.
>
> Thanks.
>
>
> Bob
>
>
> Robert Barr
> Manufacturing Engineering
> Formation, Inc.
> Voice: 856-234-5020 x3035
> Fax: 856-234-6679
> email: [log in to unmask]
>
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> ------------------------------
>
> End of TechNet Digest - 29 Mar 2001 to 30 Mar 2001 - Special issue
(#2001-193)
>
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