Rudolph,
I hate the "Double Reflow" name for these type of failures. IBM coined the
name since they saw the defect the second time the soler became molten.
Their surface mount reflow joints were perfect and then some of them "broke"
when they wave soldered. These brittle fractures don't have to happen the
second time they melt and in fact we don't believe they happen when the
solder melts. We believe they happen when the solder solidifies. We have a
case where there are three 244 I/O leaded packages on a single sided surface
mount product. The boards sees only one forced convection reflow and no
wave soldering. We see a brittle fracture on one corner pin of only one of
the three packages. At room temperature a solder joint can withstand a
considerable stress without breaking. Typical gull wing lead surface can
take about 1Kg of vertical pull force before the solder joint breaks. At
elevated temperature they can not withstand as much stress. The breaking
force decreases linearly with temperature. At or near the liquidus
temperature the solder joint is extremely sussceptable to brittle fractures.
This is also the time when the board has the most stress. When leads are
connected to pads on a baord by liquid solder surface tension can take
considerable movement before the liquid legament breaks. As soon as solder
solidifies the part is "anchored" and the stress is applied to the solder
joints that are solidified. If the stress is greater than the "critial"
value (which I'm not able to calculate) one or more of these joints
fracture. The wave we solved the fractures to the one lead on the three 244
I/O packages was to turn the board 180 degreees going through the reflow
oven. Because of the location of the cooling ports within the oven the
solidification changed just enough to prevent the brittle fracture.
I can't begin to tell you why some boards experience brittle fractures and
why some don't because I don't know your assembly process. My guess is that
you probaly don't wave solder individual PCI cards or pin-in-paste reflow
single boards but process them in a multiple-up subpanel. If this is the
case than not all of the boards would see identical stress and only some
boards would have fractured solder joints.
I may not be able to give a detailed technical analysis of the root cause
but I do believe that if you prevent the surface mount solder joints from
melting during wave soldering you probably won't experience brittle
fractures.
You could blame your component supplier and tell them they are selling you
bad components, or you could blame your board fabricator and tell them they
are selling you bad boards but I'm sure their response is going to be that
the problem is that your assembly process isn't in control. If "Double
Reflow" type brittle fractures are your problem then cutting the wide trace
adjacent to the BGA surface mount pad should prevent the defects but my
guess is your customers would be un-happy. If I had the problem I'd tape
off the bottom side of the board beneath the BGA to see if the problem goes
away. If it does I'd know the problem is "Double Reflow" and then I could
set about finding a solution I could live with. I don't believe taping
would be a viable ling term solution. The long term solution for our wave
solder induced "Double Reflow" problems was to lower our sodler pot to
reduce the contact length, increase our conveyor speed from 4.5 feet per
minute to 6.0 feet per minute and lower our solder temperature from 505F to
465F. This fixed our "Double Reflow" problem without decreasing our
assembly capacity.
Regards,
George
George M. Wenger DMTS
Bell Laboratories Princeton, Supply Cain Network
Engineering Research Center FMA / AQA / RCA Lab
(609) 639-2769 (Office); 3210 (Lab); 2346 (Fax)
[log in to unmask]
-----Original Message-----
From: Rudolph Yu [mailto:[log in to unmask]]
Sent: Thursday, March 29, 2001 6:02 PM
To: [log in to unmask]
Subject: [TN] BGA crack Summary, theory, and questions
I hope this is not too much for you guys. I just wish that one day I can
find out the root cause for this interesting case ( for me at least). There
are so many responses since I sent out my question yesterday. Because of my
workload, I am sorry that I cannot reply and thanks each of you.
Let me just quickly summarize my problem, and I want to share with the group
one of my theories of how this could happen. Since I don't have a EE
degree, so it may sounds funny to many of you. I want to know if this make
sense at all to you guys.
Problem: BGA Mirco -fracture was found on every 4-5K boards we built at a
same I/O. The board is a single sided with through hole connectors. (reflow
and wave) (actually we also had used the paste in hole process and see the
same failure mode).The board is FR4, 8layers with HASL finish. The same
ASIC is used on the other product with no failure reported. ( yes, the vias
routing on the fab is different between the two design)
If you are interested in this case, Stephen R. Gregory had helped me to post
my pictures at http:www.xdrive.com/share/985835366039IhSi4tEHHweAj9vYGZA6
George, Robert and several of you have pointed out the double reflow
phenomenon, and that the pad with a long trace to the via can induce stress
to the joint. A very good point.
However I just find out that our oversea contractor did also use the
paste-in-hole process as part of the experiment, ( As you see, i just picked
up the project) and some of those boards have the same problem too.
Now my first question of the day: If double reflow on the SMT joint is
indeed the root cause for the failure at this particular joint, should it
happens more frequently than 1 out of every 4-5 thousand boards we built?
How repeatable this phenomenon should be?
Now to my theory and please don't laugh if it sounds funny.
Can a current high enough to generate heat to the joint and thicken the
intermetallic layer or simply induce a crack to the joint? The failure
joint is used as an bi-polar address line which requires a very small amp.
But what if a nearby circuitry, which carry a strong current, shorts with
the trace attached to the ball because of low yield from the fab vendor (A
build-in narrow electrical spacing ) Can the intermetallic layer /joint be
affected by this?
Question:
What is the intermetallic growth rate with Tin/lead and Ni?
How much current does it needs to have to increase 1 degree C at the joint?
I am going to the CAD group to see if the trace spacing had been violated or
is abnormal on this product.
Comments, thought, or it is enough??
Anyway, thanks for taking the time reading this.
Rudolph Yu
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