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March 2001

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Subject:
From:
Rudolph Yu <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Thu, 29 Mar 2001 18:02:06 -0500
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I hope this is not too much for you guys.  I just wish that one day I can
find out the root cause for this interesting case ( for me at least).  There
are so many responses since I sent out my question yesterday.  Because of my
workload, I am sorry that I cannot reply and thanks each of you.

Let me just quickly summarize my problem, and I want to share with the group
one of my theories of how this could happen.  Since I don't have a EE
degree, so it may sounds funny to many of you. I want to know if this make
sense at all to you guys.

Problem: BGA Mirco -fracture was found on every 4-5K boards we built at a
same I/O. The board is a single sided with through hole connectors.  (reflow
and wave) (actually we also had used the paste in hole process and see the
same failure mode).The board is FR4, 8layers with HASL finish.  The same
ASIC is used on the other product with no failure reported. ( yes, the vias
routing on the fab is different between the two design)
If you are interested in this case, Stephen R. Gregory had helped me to post
my pictures at http:www.xdrive.com/share/985835366039IhSi4tEHHweAj9vYGZA6

George, Robert and several of you have pointed out the double reflow
phenomenon, and that the pad with a long trace to the via can induce stress
to the joint.  A very good point.
However I just find out that our oversea contractor did also use the
paste-in-hole process as part of the experiment, ( As you see, i just picked
up the project) and some of those boards have the same problem too.

Now my first question of the day:  If double reflow on the SMT joint is
indeed the root cause for the failure at this particular joint, should it
happens more frequently than 1 out of every 4-5 thousand boards we built?
How repeatable this phenomenon should be?

Now to my theory and please don't laugh if it sounds funny.

Can a current high enough to generate heat to the joint and thicken the
intermetallic layer or simply induce a crack to the joint?  The failure
joint is used as an bi-polar address line which requires a very small amp.
But what if a nearby circuitry, which carry a strong current, shorts with
the trace attached to the ball because of low yield from the fab vendor (A
build-in narrow electrical spacing )  Can the intermetallic layer /joint be
affected by this?

Question:

What is the intermetallic growth rate with Tin/lead and Ni?
How much current does it needs to have to increase 1 degree C at the joint?

I am going to the CAD group to see if the trace spacing had been violated or
is abnormal on this product.


Comments, thought, or it is enough??

Anyway, thanks for taking the time reading this.

Rudolph Yu

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