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March 2001

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Subject:
From:
Rudolph Yu <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 28 Mar 2001 14:31:15 -0500
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text/plain (117 lines)
Hi Bob

Yes we did a cross section of that row on several RMA boards, the grain
structure of that cracked ball looks just as pretty as the others next to
it.  The I/O is an address line and is not connected to the ground plane.
The failure rate acutally is 0.02% .  So most of our products we built
through the the same process do not see this problem.

Thanks for replying my email
Rudolph



------Original Message------
From: Bob Perkins <[log in to unmask]>
To: [log in to unmask]
Sent: March 28, 2001 6:09:57 PM GMT
Subject: Re: [TN] BGA crack- major headache


Hi
Have you had a look under the BGA of the reflow quality on that perticular
ball, does it look nasty on the microscope; too much heat, or maybe this
ball has not enough heat.  If the reflow on the bga is not even I would
sugest slowing down the profile and reducing the slope at spike.  Give the
bga a better chance to reflow evenly. It is quite possible to have a ball
close or attached to ground sucking up the heat, or the opposite, a ball
that has a thermal stress on it.

Bob Perkins
SMT Manufacturing Process /
Automation Technician
Aimtronics-Delta

-----Original Message-----
From: Rudolph Yu [mailto:[log in to unmask]]
Sent: Wednesday, March 28, 2001 8:48 AM
To: [log in to unmask]
Subject: [TN] BGA crack- major headache


Here are the facts:

PBGA-272 balls
FR4 with HASL finishes 8 layers

The failure point always happens at the same I/O which is the 2nd last ball
of the top outmost row of the package. It is not located near the edge of
the board or any breakaway point.

Failure mode
Micro fracture found near the intermetallic layer between the BGA package
and the solder ball attached to it.

Around 0.001% of the products we built failed in the field because of this.
None of these were caught during the ICT or Functional test.

The same ASIC is also used on several other Products and have never seen an
issue like this.  Somehow this failure mode with this ASIC only occurs in
one particular product /design.


The ASIC / fab lot-related , ICT pin interference, stress by the breakaway
tab, and stencil cleanliness assumptions had already ruled out after a
controlled lot was built few weeks back.  All boards passed the tests.  But
now some boards started failing in the field.

Why the crack always happen to one single location(ball) with the same
product we built??


We have run out all the possibilities that we can think of. I hope all the
experts in TechNet can share their opinions on this.  Customer kept asking
for the root cause analysis. Right now we just cannot came up with a
reasonable one.

Thanks
Rudolph Yu

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