TECHNET Archives

March 2001

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Rudolph Yu <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 28 Mar 2001 14:18:40 -0500
Content-Type:
text/plain
Parts/Attachments:
text/plain (109 lines)
Hi Phil:

The users' enviornment should be similar among the products using this ASIC.
But even if these failure boards were subject to extremes temperatures, why
would only 1 out of 272 balls experiences the cracking phenomenon?  At this
point I also cannot say that it is related to the process because only 0.02
% or less of the units failed in the field, and the these units are not from
the same lot.

Thanks for replying to my email

Rudolph Yu


------Original Message------
From: Phil Crepeau <[log in to unmask]>
To: [log in to unmask]
Sent: March 28, 2001 5:17:10 PM GMT
Subject: Re: [TN] BGA crack- major headache


hi,

have you checked to see if this particular product is exposed to temperature
extremes that your other products using this bga do not see?

phil

-----Original Message-----
From: Rudolph Yu [mailto:[log in to unmask]]
Sent: Wednesday, March 28, 2001 8:48 AM
To: [log in to unmask]
Subject: [TN] BGA crack- major headache


Here are the facts:

PBGA-272 balls
FR4 with HASL finishes 8 layers

The failure point always happens at the same I/O which is the 2nd last ball
of the top outmost row of the package. It is not located near the edge of
the board or any breakaway point.

Failure mode
Micro fracture found near the intermetallic layer between the BGA package
and the solder ball attached to it.

Around 0.001% of the products we built failed in the field because of this.
None of these were caught during the ICT or Functional test.

The same ASIC is also used on several other Products and have never seen an
issue like this.  Somehow this failure mode with this ASIC only occurs in
one particular product /design.


The ASIC / fab lot-related , ICT pin interference, stress by the breakaway
tab, and stencil cleanliness assumptions had already ruled out after a
controlled lot was built few weeks back.  All boards passed the tests.  But
now some boards started failing in the field.

Why the crack always happen to one single location(ball) with the same
product we built??


We have run out all the possibilities that we can think of. I hope all the
experts in TechNet can share their opinions on this.  Customer kept asking
for the root cause analysis. Right now we just cannot came up with a
reasonable one.

Thanks
Rudolph Yu

---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send the following message: SET
Technet NOMAIL
Search previous postings at: www.ipc.org > On-Line Resources & Databases >
E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send the following message: SET
Technet NOMAIL
Search previous postings at: www.ipc.org > On-Line Resources & Databases >
E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
---------------------------------------------------------------------------------

---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send the following message: SET Technet NOMAIL
Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
---------------------------------------------------------------------------------

ATOM RSS1 RSS2