Thought I would offer my two cents worth on this issue.
1) When I order PCBs I expect them to match the data I send out to within
the acceptable tolerance generally less than 20%, less than 10% variance
preferred.
2) All final inspection is made to 1:1 originals generated from the
unadjusted gerber files.
3) I do allow the fab. house to manipulate the data for process, knowing
that they will adjust for etch, shrink, etc. I also only use any Fab.
artwork for reference.
-----Original Message-----
From: Neel, Robert [mailto:[log in to unmask]]
Sent: Thursday, February 15, 2001 2:18 PM
To: [log in to unmask]
Subject: [TN] design vs reality?
Hi People,
I've had technet streaming into my terminal for a couple of weeks now and
thoroughly appreciate the background flow of information.
I have a question for any interested participant: What causes a finished
circuit board pattern/trace to deviate from the photoplot?
I'm looking at the photoplot file of a critical section of a circuit board
I'm trying to field. The plot file shows a pad-to-ground clearance of 20
mils. And yet when I slap a finished board under the scope, the
pad-to-ground clearance measures 15-mils from one supplier and 10-mils from
another. (The component center-to-center patterns are correct, so it's not a
matter of scaling.)
What gives?
The assembly people are pounding on me to open-up the clearance, but, for
the application constraints, and, by the book, the design clearances are
fine.
Is this correct? Will the finished PCB deviate so wildly from my plots?
How much deviation can I expect? How much compliance can I demand? What's
a reasonable difference between the photoplot file content and the finished
board?
(If you want to make my day, tell me they should match exactly. Then tell me
why they might not match and by how much.)
Thanks in advance.
Robert
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