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February 2001

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Subject:
From:
Phil Nutting <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Thu, 15 Feb 2001 14:50:14 -0500
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Robert,

Not that your vendors have done this, but one of our vendors was "saving" us
money by using a silk screen process to apply the board design on the copper
rather than the "more expensive" photo transfer method.  We had traces that
"grew wider" between component pads and caused solder shorts.

The solution was to tell Purchasing that the lowest price was not always a
good thing and tell the vendor to use the "more expensive" method of
applying the board design.  That coupled with having CAD reduce the amount
of exposed copper in the solder mask has made this one board manufacturable
without shorts.

This is just one engineer's experience.

Regards,

Phil Nutting
Manufacturing Engineer
Kaiser Systems, Inc.
High Voltage Power Supplies That Work(tm)
126 Sohier Road
Beverly, MA 01915
ph: 978-922-9300
fx: 978-922-8374
[log in to unmask]


-----Original Message-----
From: Neel, Robert [mailto:[log in to unmask]]
Sent: Thursday, February 15, 2001 2:18 PM
To: [log in to unmask]
Subject: [TN] design vs reality?


Hi People,

I've had technet streaming into my terminal for a couple of weeks now and
thoroughly appreciate the background flow of information.

I have a question for any interested participant: What causes a finished
circuit board pattern/trace to deviate from the photoplot?

I'm looking at the photoplot file of a critical section of a circuit board
I'm trying to field.  The plot file shows a pad-to-ground clearance of 20
mils.  And yet when I slap a finished board under the scope, the
pad-to-ground clearance measures 15-mils from one supplier and 10-mils from
another. (The component center-to-center patterns are correct, so it's not a
matter of scaling.)

What gives?

The assembly people are pounding on me to open-up the clearance, but, for
the application constraints, and, by the book, the design clearances are
fine.

Is this correct?  Will the finished PCB deviate so wildly from my plots?
How much deviation can I expect?  How much compliance can I demand?  What's
a reasonable difference between the photoplot file content and the finished
board?

(If you want to make my day, tell me they should match exactly. Then tell me
why they might not match and by how much.)

Thanks in advance.

Robert

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