Gabi,
My opinion is any tombstoning is unacceptable.  You
can track it anyway you want, but you should be able
to eliminate it completely. You may want to revisit
the stencil design.  Using homeplate appertures?
Getting the point of the paste under the part?  Once
again, check the profile.  You may have to adjust the
belt speed a bit to help this.  The one time I had
tombstone problems I adjusted apperture position so I
knew I had paste under the part when it was placed and
adjusted belt speed.  This cured the problem.

Brad Kendall
--- Bogdan Gabi <[log in to unmask]> wrote:
> Hi, Technetters
> As we moved to smaller ceramic multilayer capacitors
> and resistors,(0603)we
> encounter an increase of tombstoning .
> We checked our process-printing, reflow, layout, and
> did not find any other
> clues but the component solderablity- so it seems.
> Due to very populated boards, the defect is seen
> quite often per board, but
> usually only one component /board.
> Could you please tell me what is the acceptable
> number of this kind of
> defect, and how you record it, per board or per
> solder joints?
> Thank you,
> Gaby
>


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