Whoops. Tuan is right. -MH
> ----------
> From: Tuan Le[SMTP:[log in to unmask]]
> Sent: Wednesday, February 07, 2001 5:03 PM
> To: 'TechNet E-Mail Forum.'; 'Hiteshew, Michael'
> Subject: RE: [TN] Controlled Impedance
>
> I believe the Polar CITS25 costs ~ $800 (not less than $100 - maybe
> Michael meant < $1000).
>
> -----Original Message-----
> From: Hiteshew, Michael [ mailto:[log in to unmask]]
> Sent: Wednesday, February 07, 2001 1:38 PM
> To: [log in to unmask]
> Subject: Re: [TN] Controlled Impedence
>
>
> Tom,
> For starters, read through IPC-2221, sec 6.4. Then consider
> getting
> a copy of IPC-D-317A and/or IPC-2141, both of which deal with high speed
> design. Also, Polar Instruments sells a really nice impedance modeler,
> CITS25, for less than $100. It's worth its weight in gold. Buy it. Here're
>
> some rules of thumb:
> 1. Plan:
> A) Plan where you're going to put the parts.
> B) Plan your layer stackup: Which layers will be power/gnd planes and
> which
> layers you're going to route the controlled impedance traces on. You will
> need to make these layers adjacent to a gnd plane. If you have a lot of
> controlled impedance traces, consider dedicating two or four layers just
> for
> that.
> 2. Route them efficiently:
> A) Route the controlled impedance traces first. If you're putting them in
>
> an autorouter, give them the highest priority, followed by clocks, control
>
> lines, data lines and address lines (in that order).
> B) Minimize the number of layer changes you make when routing. If you
> must
> change layers, move from one side of a gnd plane to the opposite side of
> that same gnd plane. There is a high speed return path on the gnd plane
> trying to run parallel to the signal pulse. If you move the signal from
> being adjacent to one plane, then adjacent to a different plane, the
> return
> pulse may need to take a very circuitous path trying to get back parallel
> to
> the signal pulse. That can cause EMI/RFI problems. This is especially true
>
> for PCBs with split planes.
> 3. Generate a communicative Fab drawing.
> A) Create a detailed chart on your Fab drawing telling the manufacturing
> engineers exactly how the board is modeled. Include the following in the
> chart as a minimum:
> 1. Trace width.
> 2. Layer(s)
> 3. Ground plane(s) to which the impedance is referenced.
> 4. Upper dielectric spacing.
> 5. Lower dielectric spacing.
> 6. Target impedance +/- 10%.
> 7. Dielectric constant you used.
> B) Generate a detailed stackup cross-section view.
> C) Include a note giving the manufacturing folks leeway to change trace
> widths, spacing and dielectric thickness as required. Every batch of
> material and every process is unique and they'll need to tweak your
> numbers
> (I guarantee it :>) ).
> Good luck,
>
> Michael Hiteshew
> Lockheed Martin NE&SS Marine Systems
> [log in to unmask]
>
>
>
>
>
>
> > ----------
> > From: Tom Colby[SMTP:[log in to unmask]]
> > Reply To: TechNet E-Mail Forum.;Tom Colby
> > Sent: Wednesday, February 07, 2001 10:52 AM
> > To: [log in to unmask]
> > Subject: [TN] Controlled Impedence
> >
> > Hello Technetters,
> >
> > I'm about to embark on a PWB design involving controlled impedence but
> > feel
> > I may be a little lacking on the subject. Could someone offer to share
> the
> > "dos and don'ts" or point me to the resources I'd need to educate
> myself?
> >
> > Thanks, in advance,
> >
> > Tom
> >
> >
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