We are forced to do that too, but only in the high-speed sections of the design.

A double trace will not increase inductance, it will decrease, and at high speeds
the voltage drop can be significant so your engineer does have a point.

On the other side of the coin, however, the if you calculate the equivalent
"trace width" of a via, which is its diameter times pi (13 x 3.14159), you
aren't gonna see much inductance through the via, since it is like 40 mils,
you get most of it in the trace from pad to via, which is only 10 mils.
So why not simply increase the trace width? And (if you are tenting vias)
move the via very close to the pad?
We haven't seen any soldering problems with fat traces if the mask is good.

Good Luck,
Jack

 -----Original Message-----
From:   Jeff Seeger [mailto:[log in to unmask]]
Sent:   Friday, December 01, 2000 11:40 AM
Subject:        Re: Strange cap Layout

> "Kuczynski, Michael @ SPACENAV" wrote:
> >
> > I have an engineer who wants to place 2 vias per side on a 0508 capacitor
> > for decoupling. (I tried to draw figure below)
> > He says it will help in filtering and if it isn't done, then don't bother
> > putting any caps on (idle threat)
> > The fanout trace is .010 / via is an .013 / SMT pad is .035 x .080 / spacing
> > between vias is .0625 (center2center)
> > I think it's horse-hockey and will introdure more inductance, beside taking
> > up routing channels
> > I'm looking for any support pro or con on this configuration.
> >
> >       -------     -------
> > o----|      |     |      |----o
> >      |      |     |      |
> > o----|      |     |      |----o
> >       ------      -------
> >

        Michael,

        Your other responses are correct but here's a little more
        information.  The mounted inductance of the capacitor is
        quite an issue at speeds much above 100MHz.  The higher
        the edge rates of concern, the more correct the comment
        about not putting them on becomes.  The easiest way to
        look at this mounted inductance is considering the loop
        from the power via to the ground via.  The best way to
        decrease this inductance with normal vias would be thus:

               ()     ()
               ||     ||       <= trace as wide & short as possible
> >       -------     -------
> >      |      |     |      |
> >      |      |     |      |
> >      |      |     |      |
> >       ------      -------

        This arrangement will produce about the same mounted in-
        ductance as your dual tie setup if routed as you've shown.
        (ref Tanmoy Roy, Larry Smith, "ESR and ESL of Ceramic
        Capacitor Applied to Decoupling Applications", Proceedings
        of 1998 EPEP, West Point NY, October 26-28 1998, pp 213-216)

        Adding a 2nd tie on the opposite side will halve that
        mounted inductance yet again (a good thing).  The best con-
        nection possible is to put the vias in the pads, at the in-
        side - of course this is usually not practical.

        HTH,
--

      Jeff Seeger                         Applied CAD Knowledge Inc
      Chief Technical Officer                  Tyngsboro, MA  01879
      jseeger "at" appliedcad "dot" com                978 649 9800

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