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December 2000

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Subject:
From:
Jim Kittel <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Fri, 15 Dec 2000 07:47:05 -0700
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I continue to be amazed by how much experience and technical expertise there
is silently monitoring TechNet.  I wish to thank all the contributors for
their knowledgeable inputs.  The 'via heat path' and 'adjacent joint stress
fractures' sounds like a model that describes what I am seeing.  This model
also predicts why the failures occur on QFP's with flexible leads and not on
chips or components with heavy leads.

I do have vias and short traces attached to those pads and intend to do a
more thorough investigation of the artwork to try to predict this on future
boards.  Then maybe some design guidelines can be put in place (Steve).  Our
boards are pretty complex, 10 - 20 layers impedance control with many 1
ounce (sometimes 2 ounce) planes.

Masking, aluminum heatsinks, or selective pallets would work on this
particular board (and we are building a pallet now), but we run other mixed
technology boards thru wave solder with double sided SMT components that may
be seeing the same problem.  It is a difficult problem to locate visually
and at this time I am not sure how to predict it's occurrence.  The first
board was found in functional test.

Jowan suggested running a hotter wave solder profile which I will try.  I
wonder if anyone has tried covering the via lands with solder mask (not
tenting the via).  We do that now with LPI on the top side to protect BGA's.
The solder mask may provide enough thermal insulation to prevent sufficient
heat flow to the QFP pads?

Thanks for the help, I will let you know how we do,

Jim Kittel
L-3 Communications
[log in to unmask]

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