Frank,
IPC-2222, Sec. 10.1.1 covers edge spacing, and refers to IPC-2221, Table
6-1, with an additional 0.4mm clearance (not considering using card
guides). Using table 6-1, for internal conductors, voltages under 15V peak
(AC or DC), min electrical conductor spacing is 0.05mm for a bare board.
So the min clearance per IPC for this example is 0.45mm [0.0177"].
A designer also needs to add to that the negative tolerance range for the
pcb border for fabrication tolerance. If the tolerance is say +/-0.010
(total tolerance range is 0.020), 0.018 + 0.010 = 0.028 (rounded) would be
needed, minimum, as a clearance on an inner-layer.
Hope it helps...
Roger M. Stoops, C.I.D., PCB Designer
Spectra Precision Inc./Trimble Navigation Ltd.
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: 937.233.8921 or 937.233.4574 ext 288
Fax: 937.233.7511
Franklin D Asbell
<fasbell@NETWORKCIR To: [log in to unmask]
CUITS.COM> cc:
Sent by: TechNet Subject: Re: [TN] Exposed power-ground plane
<[log in to unmask]>
10/05/88 01:33 PM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Franklin
D Asbell
But what specification would this fall under...IPC 6012? A-600? I've
reviewed both
and even went back into D-275 to no avail. I did read a paragraph about
internal
layers must meet the same criteria for outer layers but nothing close to
what I was
expecting to see in these documents.
Any direction from the gang would be wonderful
Franklin
Brooks Bill wrote:
> Hi Frank...
>
> Well... if the board had been laid out properly.... you would not see any
> power or ground where there was a beveled edge...
> The designer of the board should make a minimum clearance around the
entire
> board outline to allow a gap between the power/gnd planes and the board
> edge... in the area where there is to be a beveled edge it may need to be
a
> greater gap than the rest of the perimeter...
> Most of the board houses I have talked with like to see a .050 min. gap
> between the edge of the board and the internal planes or circuits. Or any
> circuits for that matter... top or bottom. this allows a good adhesion of
> the laminate and prevents shorting between the layers, if the board comes
> into edge contact with any conductive medium. And it's good design
> practice... too. Of course, there are exceptions... edge contacts need to
> come to the edge... etc... but in the illustration you sent below, these
> are internal planes and should not be exposed by the chamfering process.
>
> Bill Brooks
> Senior PCB Designer - [log in to unmask]
> Zoneworx, Inc.
> 40925 County Center Drive, STE 200
> Temecula, CA 92591
> http://www.zoneworx.com
> Tel: (909) 296-1226 x 1037
> Co-Director / Education Officer / Webmaster
> for the San Diego Chapter of the IPC Designers Council
> http://www.ipc.org/SanDiego/index.html
> http://home.fda.net/bbrooks/pca/
>
> -----Original Message-----
> From: Franklin D Asbell [mailto:[log in to unmask]]
> Sent: Wednesday, October 05, 1988 9:36 AM
> To: [log in to unmask]
> Subject: [TN] Exposed power-ground plane
>
> I need some input from all of you...
>
> What specification provides criteria for power-ground planes being
> exposed due the bevel process, or actually exposed planes for any
> reason?
>
> Or does anyone know the specific criteria, dimension, tolerance, etc for
> this condition.
>
> ----------
> ------------\- < exposed power layer
> ------------/- < exposed ground layer
> ----------
>
> Thanks,
>
> Franklin D Asbell
>
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