Hi,

A sort of related question which someone hopefully can shed some light on.

For resin plugged thru vias and filled buried vias,
what is the acceptable limit on the amount of voiding and
the maximum acceptable size of a void,
in terms of  % by volume of the via cavity?
I have assumed a normal surface mount assembly process environment.
Any reference to a helpful specification / article would be most welcome.

Many thanks,

Barry Bates
BAE SYSTEMS


-----Original Message-----
From:   Franklin D Asbell [SMTP:[log in to unmask]]
Sent:   30 October 2000 23:35
To:     [log in to unmask]
Subject:        Re: [TN] Plugging (not tenting) of via fab notes

                   *** WARNING ***



It's a little confusing...but then I'm not the expert.

In regards to exposed vias...the artwork will dictate what vias are to
be exposed and/or plugged so the mention of that in the notes may
confuse the issue. Stating Green LPI IAW SM-840 should be enough in most
cases I would suspect. Your comment on 'associated vias'...what exactly
are 'associated vias? Is this all vias on a commen net?

Hope the critique helps some.

Franklin



Ken Patel wrote:
>
>         Fab Expert,
>         Is the following fab note make sense to you or should I also mention
> the plugging side as I do not want higher surface on fine-pitch side. Also,
> comment on use of SR1000 epoxy in my fab note.
>
>         SOLDERMASK: GREEN PHOTOIMAGEABLE, BOTH SIDES PER IPC-SM-840, CLASS
> 3. ALL TEST-VIAS AND ASSOCIATED PADS ARE TO BE FREE OF SOLDERMASK. ALL
> NON-TEST VIA HOLES TO BE PLUGGED WITH SR1000 OR EQUIVALENT EPOXY.
>
> re,
> ken patel
>

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