This going to be my 2 cents worth. My bet this is an area where "real
world" situations come in to play. Design standards/specs are developed to
be used by design engineers to produce a good design eliminating reliability
problems and enhancing manufacturability of assemblies.
Stacking should only occur when a "fix" is needed to improve the electrical
design after the initial design the same as we did with through hole or
relays problems. (Noise is probably the reasons for capacitor and diode
shunts and stacking to change values) When the board are re-laid out which
should occur after initial design then the piggy back components, jumper
wires, etc should go away. I just cannot envision the use of stacking of
components during the first lay out of the assemblies by the engineers.
Again just my opinion, Jon
-----Original Message-----
From: Clive ffitch [mailto:[log in to unmask]]
Sent: Friday, October 20, 2000 4:59 AM
To: [log in to unmask]
Subject: [TN] IPC Standards on Stacked Chip Components
All,
I've searched the TechNet archives and only found similar confusion.
From my perspective in electronics packaging design, I am looking for
standards/documented reasons (evidence for others - you know how it
is!) NOT to stack chip resistors/capacitors. Reasons basically boil
down to reliability concerns for high-rel use, and I am advising
against such courses of action.
The issue is where stacking of components might be covered in the IPC
specs. The only reference I have been able to find is in the now
superceded IPC-D-275, in para. 4.4.2.1 "End-Capped Discrete components"
which quite catagorically states "...shall not be stacked, nor shall
they bridge spacing between other parts or components... see Figure
4-38". The figure is equally explicit.
However, when I consult the new IPC-2221 Printed Board Design Standard,
I find all this has gone! The only reference I now find in its place,
is in the latest Rev.C of IPC J-STD-001 in para. 6.4.2.1 "Mounting of
Parts on Parts (Stacking)" which states "When part stacking is
permitted by the assembly drawing/documentation, parts shall not
violate minimum electrical clearance...". This now implies that even
for Class 3, if its on the drawing you can do it. Which means you can
still put it on the drawing for high-rel Class 3 and do it, as long as
you don't short it out! Which rather neatly avoids the issue and
bounces it back on the user of the Standard.
So, why has the clear statement against this gone from the IPC design
standard? Does the IPC - and the rest of industry - think that stacking
components for Class 3 is now OK?
For our own case in point, I have advised adhesively mounting the
additional chip locally to the first, and using jumper wires.
Regards,
Clive ffitch
MBUK
Stevenage, England
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