> Yes, but isn't that what a netlist test is doing as
> well...comparing where the data
> say's a trace is supposed to be against the actual
> board itself (ET)...comparing how
> wide a space, or thick a trace is supposed to be
> against the board itself (AOI).

No, that isn't exactly what the netlist is doing.  The
netlist or ET has a list of which traces are supposed
to be connected (and conversely what shouldn't be
connected). The test doesn't care it the trace is
.006"  or .00006" wide. It only cares that there is a
connection.  Using this as an example it would in fact
be better to have the outer layers AOI'd because the
ET wouldn't detect a defect.

>
> Now in both of these the goal is to verify the
> product meets requirements.... So....to
> stir things up again (it's Saturday, 6:00 AM and I'm
> feeling the need I supposse
> ~grin~) as long as I ensure I meet customer
> requirements, what difference does it make
> whether I use our bed-of-nails, flying probe, AOI,
> enhanced visual, etc...as long as
> the board meets the need of the customer?

<bear with me, I have a story to tell>
I had occasion several years ago of sending cores to a
'service bureau' to have the cores AOI'd.  Cores came
back as 'good' we pressed them and kept coming up with
shorts.  Not just an occasional short but shorts on
many panels.  The bottom line was that, according to
the service bureau, the AOI doesn't see narrow traces
when they are embedded between wide traces.  In this
case there were .010" traces between .050" traces.>

So, with this story in mind there may be traces that
aren't even seen.  <Ok, all of the AOI experts out
there can chime in to correct/confirm my story>

Two final points.  A defect has to be a specific size
to be seen by AOI.  I don't know what that size is but
it is large enough that an open would not be detected.
And, finally AOI is slow.  (Compared to a grid test).

Just my two cents worth...

pete





>

> Franklin D Asbell
> Network Circuits, Inc.
> Irving, Texas
>
> Peter Menuez wrote:
>
> > Franklin,
> >
> > Besides the problems with AOI that have been
> addressed
> > in several other emails there is a potential
> problem
> > of the AOI itself.  Most of the AOI's that I am
> > familiar with use 'design rule' checks rather than
> an
> > actual comparison of real data to real product.
> >
> > Maybe someone out there in Technet Land could
> expand
> > on design rule checking because I don't know much
> > about it, but this alone would make me nervous.
> >
> > Pete
> >
> > --- Franklin D Asbell
> <[log in to unmask]>
> > wrote:
> > > Just read an article in "The Board Authority"
> > > regarding Automatic
> > > Optical Test (AOT).
> > >
> > > Just wondering what you assemblers or purchasers
> of
> > > bare boards thoughts
> > > are on fabricators performing 'optical testing'
> > > (visual, AOI)  instead
> > > of 'contact testing' (BON, probe)????
> > >
> > > An example: You state all boards to be
> electrically
> > > tested for
> > > opens/shorts, and instead of throwing the boards
> on
> > > our flying probe or
> > > bed-of-nails equipment I decide to put this on
> my
> > > AOI after setting it
> > > up to flag for opens/shorts, would you be
> satsified
> > > with this method?
> > >
> > > Franklin D Asbell
> > > Network Circuits, Inc.
> > > Irving, Texas 75061
> > >
> > >
> >
>
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