> Date: Tue, 5 Sep 2000 08:55:21 -0700
> Reply-to: Combined Forum of D-33a and 7-31a Subcommittees
> <[log in to unmask]>,
> "Knapp, Clarence W." <[log in to unmask]>
> From: "Knapp, Clarence W." <[log in to unmask]>
> Subject: Re: [IPC-600-6012] FW: Exposed copper
> X-To: "[log in to unmask]" <[log in to unmask]>
> To: [log in to unmask]
> I believe the intent was to set a limit on the total number of exposed
> circuits. that is count the number of trace exiting the solder mask and then
> take percentage. So a board with 1000 surface pads can have 10 incidents of
> exposed copper traces between the mask and pad.
>
> Clarence W Knapp
> M&P Engineering
> Ph 818 715-2478
> Fax 818 715-4986
> E-mail [log in to unmask]
>
>
> > -----Original Message-----
> > From: C. Don Dupriest [SMTP:[log in to unmask]]
> > Sent: Tuesday, September 05, 2000 7:10 AM
> > To: [log in to unmask]
> > Subject: [IPC-600-6012] FW: Exposed copper
> > Importance: High
> >
> > Greetings all,
> > We have an urgent request from a 6012 user. Product is being held up for
> > shipment.
> >
> > The email below and attached photo is a request for interpretation
> > concerning a manner of exposed copper. Does anyone recall the original
> > thinking behind the 3.5.4.6 on how to property apply the percentage of
> > conductor surface. My notes show no prior discussion on this paragraph.
> > See the question below in the original email.
> >
> > I believe the cause resulted from a combination of selective tin strip and
> > solder mask clearance. A small portion of the conductor is exposed with
> > bare copper. Touchup would be cost prohibitive. Does the specified
> > paragraph best cover this issue? Anyone crossed this bridge before?
> >
> > " 3.5.4.6 Final Finish Coverage Final finish shall meet the solderability
> > requirements of J-STD-003. Exposed copper on areas not to be soldered is
> > permitted on 1% of the conductor surfaces for Class 3 and 5% of the
> > surfaces
> > for Class 1 and Class 2. Coverage does not apply to vertical conductor
> > edges. "
> >
> > The bottom line is: "is this an acceptable condition"??????
> >
> > Please reply to "all" to capture the discussion.
> >
> > Thanks, hope everyone will be able to make Miami next week.
> >
> >
> > C. D. (Don) Dupriest
> > Lockheed Martin Missiles and Fire Control - Dallas
> > Electronics Manufacturing Engineering
> > Mgr. - PWB Process Development
> > Ph. 972/603-7724 fax: 972/603-3548
> > Email: [log in to unmask] <mailto:[log in to unmask]>
> >
> >
> > ----------
> > From: Cirtech [SMTP:[log in to unmask]]
> > <mailto:[SMTP:[log in to unmask]]>
> > Sent: Friday, September 01, 2000 12:13 PM
> > To: [log in to unmask] <mailto:[log in to unmask]>
> > Subject: FW: Exposed copper
> >
> >
> >
> >
> > -----Original Message-----
> > From: Mark Alexander
> > Sent: Friday, September 01, 2000 8:30 AM
> > To: 'Don Dupriest'
> > Subject: Exposed copper
> >
> > Don,
> > I've attached a picture of an area that is typical of an exposed copper
> > area. This is The trace that leads into a SMT pad that is not covered by
> > soldermask. The actual dimension of exposed copper is approx. .003 to .005
> > mils. According to ipc-6012 section 3.5.4.6 there is an allowable amount
> > of
> > exposed copper of 1% or 5% depending on what class the board is called
> > for.
> > My question is, how do you calculate this. How do you translate 1% or 5%
> > of
> > conductor surfaces. Is it total square inches of copper on board
> > multiplied
> > by 1% or 5%? If so then the formula for a board with a total of 5 square
> > inches multiplied by 1% = .050". What then do you do with the .050'.? If
> > it
> > was 5% then = .250'. What do you do with that?
> > Please fill me in
> > Thanks,
> > Mark Alexander
> > Engineering Mgr.
> > Cirtech Inc.
> > Orange, Ca.
> > 714-921-0860 ext. 220
> > <<copper.bmp>> << File: copper.bmp >>
>
To all concerned, regarding the .003-.005" exposed copper from edge
of soldermask to SMT pads. In IPC-6012, the allowable exposed copper
is 1% or 5% of the conductor surfaces. For the example given of 5
square inches, the 5sqin x .01 (1%) equals .050 INCHES SQUARE. (NOT
.05") If the .003'' exposure typical is across a .010" wide trace,
the resultant is .0003 inche square If we divide the .050 in. sq by
.0003 in. sq., then we are allowed ~167 occurrences per board.
Likewise for 5%, the allowable is .250 sq. in. divided by .0003 sq.
in. or ~833 occurrences per board. These were standard allowances
from the J-STD's that were presented to the IPC-6012 committee
members, and we did not consider them to be excessively restrictive,
as the above math shows. The bigger question is "Whatever happened
to first-article inspection, that allowed this condition to occur in
the first place?"
Being much more pragmatic, if the soldermask was put on first, and
then the part was hot-air-leveled (HAL), what "appears" as exposed
copper could in fact be a thin coat of soldermask on the circuitry
which did not allow the HAL to adhere. This is an acceptable
condition, since it is not really "exposed copper". In a circuit
board shop this is easily tested--by using a beaker of the inner
layer oxide treatment chemistry, and cotton-swabbing the questionable
areas--if they do turn dark, it is exp. cu, and if not it is
acceptable due to it being thin S.M..
If the board was selective-strip SnPb, S.M., and then reflowed, you
could have exp. cu. due to misregistration. An allowable rework
would be to HAL the entire board to cover the exposed copper. There
is nothing is the IPC-6013 that dictates how the board must be
fabricated, and selective strip, SM, HAL, is an acceptable production
technique--sometimes even called out that way by some customers.
If Cirtech does not have their own HAL, there are numerous contract
facilities in the area to do HAL.
Alternatively, the boards could be re-soldermasked using a smaller
aperature to generate the artwork--if thickness of SM was not an
issue--that will cover the exp. cu. Sure beats hand touch-up with a
soldering iron, which would be an acceptable rework.
Regards,
Dennis J Cantwell
Dir-QA Eng
Printed Circuits Inc.
612-888-7900
(member of numerous IPC committees)
|
