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| Date: | Tue, 5 Sep 2000 12:44:31 -0500 |
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Forgot to say also that when the solder for the part is reflowed, it will
probably tin the trace then.
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From: Bakke, Steve
Sent: Tuesday, September 05, 2000 12:31 PM
To: [log in to unmask]; 'C. Don Dupriest'
Subject: RE: [IPC-600-6012] FW: Exposed copper
Mr. Gendreau makes a good point. Copper edges always have been
allowed.
There is section 3.3.8 that allows on Class 3 boards a .031" gap
between the gold of an edge connector and a tinned trace.
I don't see a picture of this in IPC-A-600.
There is a picture of skipping solder mask which is allowed on Class
1 ( shows bare copper), but not on Class 3.
Maybe the big question is " are they going to conformal coat the
board after assembly?".
There has always been the added expense for SMOBC of stripping all
the tin off and then HASL. This was done because the Military believed the
exposed copper would be a reliability problem because the trace would
corrode away. Where tin plated copper runs and component leads would last
for 20 years.
Steve Bakke C.I.D.
President , Midwest Chapter, IPC Designers Council.
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From: C. Don Dupriest [SMTP:[log in to unmask]]
Sent: Tuesday, September 05, 2000 9:10 AM
To: [log in to unmask]
Subject: [IPC-600-6012] FW: Exposed copper
Importance: High
Greetings all,
We have an urgent request from a 6012 user. Product is
being held up for
shipment.
The email below and attached photo is a request for
interpretation
concerning a manner of exposed copper. Does anyone recall
the original
thinking behind the 3.5.4.6 on how to property apply the
percentage of
conductor surface. My notes show no prior discussion on
this paragraph.
See the question below in the original email.
I believe the cause resulted from a combination of selective
tin strip and
solder mask clearance. A small portion of the conductor is
exposed with
bare copper. Touchup would be cost prohibitive. Does the
specified
paragraph best cover this issue? Anyone crossed this bridge
before?
" 3.5.4.6 Final Finish Coverage Final finish shall meet the
solderability
requirements of J-STD-003. Exposed copper on areas not to be
soldered is
permitted on 1% of the conductor surfaces for Class 3 and 5%
of the surfaces
for Class 1 and Class 2. Coverage does not apply to vertical
conductor
edges. "
The bottom line is: "is this an acceptable condition"??????
Please reply to "all" to capture the discussion.
Thanks, hope everyone will be able to make Miami next week.
C. D. (Don) Dupriest
Lockheed Martin Missiles and Fire Control - Dallas
Electronics Manufacturing Engineering
Mgr. - PWB Process Development
Ph. 972/603-7724 fax: 972/603-3548
Email: [log in to unmask]
<mailto:[log in to unmask]>
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From: Cirtech [SMTP:[log in to unmask]]
<mailto:[SMTP:[log in to unmask]]>
Sent: Friday, September 01, 2000 12:13 PM
To: [log in to unmask] <mailto:[log in to unmask]>
Subject: FW: Exposed copper
-----Original Message-----
From: Mark Alexander
Sent: Friday, September 01, 2000 8:30 AM
To: 'Don Dupriest'
Subject: Exposed copper
Don,
I've attached a picture of an area that is typical of an
exposed copper
area. This is The trace that leads into a SMT pad that is
not covered by
soldermask. The actual dimension of exposed copper is
approx. .003 to .005
mils. According to ipc-6012 section 3.5.4.6 there is an
allowable amount of
exposed copper of 1% or 5% depending on what class the board
is called for.
My question is, how do you calculate this. How do you
translate 1% or 5% of
conductor surfaces. Is it total square inches of copper on
board multiplied
by 1% or 5%? If so then the formula for a board with a total
of 5 square
inches multiplied by 1% = .050". What then do you do with
the .050'.? If it
was 5% then = .250'. What do you do with that?
Please fill me in
Thanks,
Mark Alexander
Engineering Mgr.
Cirtech Inc.
Orange, Ca.
714-921-0860 ext. 220
<<copper.bmp>><<File: copper.bmp>>
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