I believe the intent was to set a limit on the total number of exposed
circuits. that is count the number of trace exiting the solder mask and then
take percentage. So a board with 1000 surface pads can have 10 incidents of
exposed copper traces between the  mask and pad.

   Clarence W Knapp
        M&P Engineering
     Ph       818 715-2478
   Fax       818 715-4986
E-mail   [log in to unmask]


> -----Original Message-----
> From: C. Don Dupriest [SMTP:[log in to unmask]]
> Sent: Tuesday, September 05, 2000 7:10 AM
> To:   [log in to unmask]
> Subject:      [IPC-600-6012] FW: Exposed copper
> Importance:   High
>
> Greetings all,
> We have an urgent request from a 6012 user.  Product is being held up for
> shipment.
>
> The email below and attached photo is a request for interpretation
> concerning a manner of exposed copper.  Does anyone recall the original
> thinking behind the 3.5.4.6 on how to property apply the percentage of
> conductor surface.  My notes show no prior discussion on this paragraph.
> See the question below in the original email.
>
> I believe the cause resulted from a combination of selective tin strip and
> solder mask clearance.   A small portion of the conductor is exposed with
> bare copper.  Touchup would be cost prohibitive.  Does the specified
> paragraph best cover this issue?  Anyone crossed this bridge before?
>
> " 3.5.4.6 Final Finish Coverage Final finish shall meet the solderability
> requirements of J-STD-003. Exposed copper on areas not to be soldered is
> permitted on 1% of the conductor surfaces for Class 3 and 5% of the
> surfaces
> for Class 1 and Class 2. Coverage does not apply to vertical conductor
> edges. "
>
> The bottom line is: "is this an acceptable condition"??????
>
> Please reply to "all" to capture the discussion.
>
> Thanks, hope everyone will be able to make Miami next week.
>
>
>         C. D. (Don) Dupriest
>         Lockheed Martin Missiles and Fire Control - Dallas
>         Electronics Manufacturing Engineering
>         Mgr. - PWB Process Development
>         Ph. 972/603-7724 fax: 972/603-3548
>         Email: [log in to unmask] <mailto:[log in to unmask]>
>
>
> ----------
> From:  Cirtech [SMTP:[log in to unmask]]
> <mailto:[SMTP:[log in to unmask]]>
> Sent:  Friday, September 01, 2000 12:13 PM
> To:  [log in to unmask] <mailto:[log in to unmask]>
> Subject:  FW: Exposed copper
>
>
>
>
> -----Original Message-----
> From:   Mark Alexander
> Sent:   Friday, September 01, 2000 8:30 AM
> To:     'Don Dupriest'
> Subject:        Exposed copper
>
> Don,
> I've attached a picture of an area that is typical of an exposed copper
> area. This is The trace that leads into a SMT pad that is not covered by
> soldermask. The actual dimension of exposed copper is approx. .003 to .005
> mils. According to ipc-6012 section 3.5.4.6 there is an allowable amount
> of
> exposed copper of 1% or 5% depending on what class the board is called
> for.
> My question is, how do you calculate this. How do you translate 1% or 5%
> of
> conductor surfaces. Is it total square inches of copper on board
> multiplied
> by 1% or 5%? If so then the formula for a board with a total of 5 square
> inches multiplied by 1% = .050". What then do you do with the .050'.? If
> it
> was 5% then = .250'. What do you do with that?
> Please fill me in
> Thanks,
> Mark Alexander
> Engineering Mgr.
> Cirtech Inc.
> Orange, Ca.
> 714-921-0860 ext. 220
>  <<copper.bmp>> << File: copper.bmp >>