Wee Mei,
In answer to your questions:
It seems that you want to consider tin/lead plating in you trace impedance
calculations, and want to create a board design up to and including
marginal design limitations. The statement made in IPC-2221 about
considering vias as internal traces may be conservative, but my experience
shows that conservative is a good place to start. For high-current traces
(>3-5 amps), I will use 2 to 6 vias when passing throught the board.
As an external trace heats up due to current flow, it will expand. It does
have some adhesion to the surface of the laminate. It also radiates heat
to free air (for what it's worth) and surrounding components/structures.
This, and other reasons that our comrades may be aware of, allows an
external trace or copper to carry more current than an internal layer.
Vias are not as fortunate. There is no adhesive holding the copper onto a
hole wall. The plating may or may not be consistent through the length of
the hole. There may be voids under the via plating. No air flow through
the hole. The via may be tented with soldermask.
Now, that said (and one cup of coffee down the hatch), tin/lead plating
adds no appreciable current carrying capacity to copper. It is possible to
decrease the impedance of a via by filling it with solder, but this becomes
a no-issue when the via size drops below say 0.015" [0.4mm]. Don't forget
that tin/lead has a resistance 8.5 times greater than copper, depending on
the tin/lead ratio. To double the current capacity of a 1 oz copper trace,
0.0014" [0.035mm] of any given width, you would need the equivalent minimum
of 8.5 ounces of tin/lead (reflowed!!) plating, or 0.012" [0.31mm]!!!
As a rule of thumb (and from personal experience), tin/lead plating should
never be used to increase the current capacity of a copper pad, trace, or
via on a pcb.
Best Regards,
Roger M. Stoops, C.I.D., PCB Designer
Spectra Precision Inc./Trimble Navigation Ltd.
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: 937.233.8921 or 937.233.4574 ext 288
Fax: 937.233.7511
Lum Wee Mei
<[log in to unmask] To: [log in to unmask]
ORG.SG> cc:
Sent by: Subject: [TN] IPC-2221
TechNet
<[log in to unmask]
ORG>
08/18/00
03:32 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Lum Wee Mei
I was checking up more information regarding my via current-carrying
capacity and found this in IPC-2221:
4.4.6 Tin /Lead Plating . . . Tin lead plating does not apply to buried
plated-through holes which are internal to the printed circuit board and
do not extend to the surface.
My questions:
1. I clearly understand the above statement when applied to buried via
but what about blind via?
2. This lead to me my previous question on why consider the plating of
a through hole/via as internal when tin/lead plating can be carried out?
I sincerely hope to receive some response from you experts out there.
Thanks and regards - Wee Mei.
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