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August 2000

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Subject:
From:
Steve Underwood <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Sun, 13 Aug 2000 21:04:07 -0400
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I sent this message to TechNet on 08/10/2000.
Did this message make it to the list?  I did not get any responses.

:-) I'm interested to know how y'all interpret IPC-2221,
:-) section 12.4.1 "Specimen A and B (Plated Hole Evaluation)..."
:-) "Spacing between holes shall be representative of the
:-) printed board.  Conductors shall be included in between the
:-) holes on each signal layer."
:-)
:-) I have the interpretation that the spacing between the
:-) holes (with the traces between them) will be determined by
:-) the worst case pad to trace spacing on the design.  So, if
:-) there are 6 mil lines and 6 mil spaces on the internal
:-) layers but only 8 mil lines and 8 mil spaces on the outer
:-) layers, I would have to set up the coupon with the 6 mil
:-) line and space throughout the entire coupon stack.  This
:-) seems to make the outer layer of the coupon then NOT match
:-) the outer layer of the board and the coupon may fail where
:-) the board may not.
:-)
:-) Do you make an extra set of A & B coupons for each
:-) different spacing configuration?
:-)
:-) Do you mix the hole to hole and pad to trace spacings on
:-) the coupons and potentially increase the size and/or
:-) complexity of the coupon?
:-)
:-) Steve

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