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August 2000

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From:
David Ricketts <[log in to unmask]>
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Date:
Fri, 11 Aug 2000 12:09:57 -0700
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I don't have any data to back my reasoning, but here goes:

I estimate a via or any hole to be roughly equivalent to a trace who's
thickness is the minimum plating and whose width is the circumference of the
hole, i.e. a 14 mil hole, 1 oz. plating is equivalent to a 44 mil trace of 1
oz. copper.

Anything wrong with this logic?

David Ricketts

Pertek Engineering
Voice: 949-475-4485
Fax:   949-475-4493

mailto:[log in to unmask]

http://www.PertekEngineering.com

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Lum Wee Mei
Sent: Thursday, August 10, 2000 10:59 PM
To: [log in to unmask]
Subject: [TN] Via current current capacity


I came across this paragraph in Printed Circuit Handbook by Clyde
Coombs, Jr stating :

"Consider a 0.04" diameter hole plated to a 2oz internal poew plane with
0.001" minimum copper in the hole. The copper hole wall is equivalent to
0.04 x 0.001 x pi = 125 x 10exp -6 sq. in.
"The copper plating of the hole wall is the smallest conductor in the
path and for purposes of calculation in current-carrying capacity,
consider it an internal conductor of a multilayer."

My questions are :
1. Why consider the copper plating of the hole wall as internal layer
and not external?
2. Is the copper plating here which is 0.001" refers to only the
electroless copper thickness or inclusive of copper plating?
3. Why is the tin-lead plating or gold plating never be considered when
calculating current-carrying capacity for component hole or via?

Hope to learn more from your experts out there.
Regards.

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