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August 2000

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Subject:
From:
Lum Wee Mei <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Fri, 11 Aug 2000 13:59:22 +0800
Content-Type:
text/plain
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text/plain (35 lines)
I came across this paragraph in Printed Circuit Handbook by Clyde
Coombs, Jr stating :

"Consider a 0.04" diameter hole plated to a 2oz internal poew plane with
0.001" minimum copper in the hole. The copper hole wall is equivalent to
0.04 x 0.001 x pi = 125 x 10exp -6 sq. in.
"The copper plating of the hole wall is the smallest conductor in the
path and for purposes of calculation in current-carrying capacity,
consider it an internal conductor of a multilayer."

My questions are :
1. Why consider the copper plating of the hole wall as internal layer
and not external?
2. Is the copper plating here which is 0.001" refers to only the
electroless copper thickness or inclusive of copper plating?
3. Why is the tin-lead plating or gold plating never be considered when
calculating current-carrying capacity for component hole or via?

Hope to learn more from your experts out there.
Regards.

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