I was checking up more information regarding my via current-carrying
capacity and found this in IPC-2221:
4.4.6 Tin /Lead Plating . . . Tin lead plating does not apply to buried
plated-through holes which are internal to the printed circuit board and
do not extend to the surface.
My questions:
1. I clearly understand the above statement when applied to buried via
but what about blind via?
2. This lead to me my previous question on why consider the plating of
a through hole/via as internal when tin/lead plating can be carried out?
I sincerely hope to receive some response from you experts out there.
Thanks and regards - Wee Mei.
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