I was also confused about the answers, as plugging or/and tenting vias was extensively
discussed before and I am sure that Steve did not miss any of that.
If I understand you well, you want to have a solder mask pattern specific for each
circuit. This is what we do here, and usually, the technologists advise the development
dep. about the vias which have to be "tented" according to the process steps and
components.Usually it is done during the first steps of the development of a new
circuit. For double reflow, we allow open vias all over, usually. We work with no
clean flux. Sometimes, changes are necessary, and the old pattern is replaced, but
then the circuit is renamed with a new version, and ordered with the new name . The
circuit manufacturers are seldom involved themselves. The purchasing department is free
to order the circuits from any approved manufacturer and provides him with the up to
date artwork.
This is what we do, maybe it does not answer your question, if so, I apologize to you
and the distinguished list.
Gaby
"Stephen R. Gregory" wrote:
> In a message dated 06/29/2000 8:09:21 PM Central Daylight Time,
> [log in to unmask] writes:
>
> > Hi Ruby,
> > There are no specifications that address this specific issue; there are
> some
> > statements in some IPC specs (cannot give them to you, because I am on the
> > road) talking about fill percentages, but that has nothing to do with PTH/
> > PTV
> > barrel wall failures. Also, when I am called in by clients with problems,
> it
> > is understandable that they do not want to publicize those.
> > Werner Engelmaier
>
> Hi Werner, Ruby, and all,
>
> This subject is what started my ranting from previous posts. If you go back
> to what I was asking about if fab vendors could fill vias during fabrication,
> I was just trying to learn if it was possible. Because we're going to be
> getting boards that will have all the vias relieved in the soldermask layer
> because of the desire for expanded ICT test coverage, but was told that it
> would be too much work to go to each and every assembly (there are a number
> of them) and relieve only the vias needed for the expanded ICT...so the easy
> solution for them would be to do a global thing to relieve all vias of the
> soldermask...no matter if the assembly still uses LCCC's and all the data out
> there is about partial via fill...(not to mention the cleaning issues)
>
> I was just ranting if this was the smart thing to do...and the fact that no
> matter how much I try to relate what I've learned from this distinguished
> list that some will ignore the facts...you guys are my buddies.
>
> Some chose to ignore the truth...the customer is always right I guess.
>
> -Steve Gregory-
>
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