John,
We have seen the PTH via crack (circumferential) which results into open
during ICT. At that moment our boards are gone thr' two reflow cycle (225c
max) and one wave cycle.

How can I select chamber profile so that it will weed out bad one? Is there
any guide lines? My boards are loaded with components and need resolution ASAP.

re,
ken patel

At 12:03 PM 7/20/2000 -0400, you wrote:
>Ken mentions:
>
>> Reliability/Quality Expert,
>> How can I select the thermal stress/shock profile for loaded board if I
>want
>> to precipitate the fab problem. Boards are functionally passed but belongs
>> to suspect date code.
>>
>> I am looking for a profile in the following format.
>
>Hi Ken,
>
>Before you do any testing, a good, root cause failure analysis is
>required before specifying a failure acceleration method.
>
>Once you've conclusively identified the specifc cause of your
>module failure, you can tailor a stress test to weed out that
>specific problem (or fix the root cause failure reason, better yet!)
>
>Without the root cause failure identified, you may end
>up spending a lot of money, and potentially ruining a lot
>of good modules  doing accelerated life/reliability testing,
>with minimal return.
>
>Rgds
>John
>
>
>-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
>John Brewer
>Supervisor, Component Engineering
>Raleigh, NC
>(919)-266-8870
>[log in to unmask]
>-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
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______________________________________________________
Ken Patel                       Phone:  (408) 490-6804
1708 McCarthy Blvd.             Fax:    (408) 490-6859
Milpitas, CA 95035

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