Werner,
What about tented vias using LPISM. And...is this done by flooding using
a dot pattern for the vias only? We typically tent using DFSM however,
at times there are requirements for LPI.
TIA,
Rick Howieson
http://www.gt-corp.com
>-----Original Message-----
>From: Werner Engelmaier [SMTP:[log in to unmask]]
>Sent: Thursday, June 29, 2000 7:17 AM
>To: [log in to unmask]
>Subject: Re: [TN] Filled via holes
>
>Hi Ruby,
>Yes, there are some concerns about PTVs partially filled with solder. The
>transition from solder-filled to non-solder-filled produces a stress riser in
>the Cu PTV barrel walls. This is of no practical concern for applications for
>which the thermal cyclic environment is not severe; for severe environments,
>e.g., automotive, military, some satellites, this stress riser can be
>enoughto cause premature failure.
>
>Werner Engelmaier
>Engelmaier Associates, L.C.
>Electronic Packaging, Interconnection and Reliability Consulting
>7 Jasmine Run
>Ormond Beach, FL 32174 USA
>Phone: 904-437-8747, Fax: 904-437-8737
>E-mail: [log in to unmask], Website: www.engelmaier.com
>
>In a message dated 6/28/00 11:19:14, [log in to unmask] writes:
>>Hello all:
>>We try to fully or partially fill the via holes (<0.025" diameter) with
>>solder due to the process. I'm wondering that if there are some concerns
>>(such as fatigue).
>>Any information are very welcome. Thanks a lot!
>>R.H.
>
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