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June 2000

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Subject:
From:
Brian Gaynor <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Fri, 2 Jun 2000 10:29:38 +0100
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text/plain
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text/plain (23 lines)
Hello all,

Anybody out there specifying plated holes at the PCB edge? This technology can
be found commonly in cyrstals. What's the fab. process steps involved (for
multi-layer)? Is there any related IPC documentation?

Brian.
J

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