John Maxwell,
Where can we find your articles about DFM?
Answer off-line if you want.
===== Original Message from [log in to unmask] (TechNet E-Mail Forum.) at
1/06/00 18:14
>Hi TechNet,
>To be precise I never recommended water jet cutting due to poor through put
>and high capitol expense. I have never been an admirer of roller blade
>cutting except when I was a consultant and it put my wife and oldest son
>most of the way through university. Ceramic capacitors are sensitive to
>cracking and becoming more so due to technology trends reducing dielectric
>thickness. Isolating parts from PWB edges is still a good idea and
>orienting MLCC parts parallel to a PWB edge helps.
>
>As a second note, in a former life I designed transistor structures for
>integrated circuits and I have a comment on X-ray. X-rays are ionizing
>radiation and can change transistor gate threshold voltages in your
>integrated circuits by damaging the gate oxide. As gate oxides get thinner
>the problem appears to get worse. I suggest that a call to your silicon
>vendors might be in order and ask them to check with their device
>designers. Some that I have talked to have expressed real concern if we get
>carried away with our X-ray machines. I have one and it is one of many
>process development and failure analysis tools.
>
>John Maxwell
>
>At 10:11 AM 6/1/00 -0700, you wrote:
>>John Maxwell discouraged using rolling blade shear but recommended water
>jet
>>cutting for depaneling. Does any body know who makes such water jet
>>cutter? Any
>>users out there who can share some experience?
>>
>>Thanks,
>>KK Chin
>>Artesyn Technologies
>>Fremont, CA
>>
>>
>>
>>
>>Gabriela Bogdan <[log in to unmask]> on 06/01/2000 09:25:55 AM
>>
>>Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please
>respond to
>> Gabriela Bogdan <[log in to unmask]>
>>
>>To: [log in to unmask]
>>cc: (bcc: KK Chin)
>>
>>Subject: Re: [TN] V-Score--stress
>>
>>
>>
>>Being one of John Maxwell's "fans" I recommend his articles about design
>for
>>manufacturability . Concerning chip capacitors, we follow as much as
>possible
>>the rules
>>, and Dwight's comments are in this spirit. Most of the failures we also
>>encountered
>>were with chip capacitors, and the separation method , the distance from
>the
>>edge, and
>>the orientation of the chip were the culprits, alone or in combination. We
>had
>>for
>>instance one panel with circuits which were manufactured first as single,
>then
>>as 4 in
>>panel. Due to the proximity of the chip cap to the edge, we had failures
>after
>>separation, and had to change the artwork accordingly.
>>Gaby
>>
>>Dwight Mattix wrote:
>>
>> > We score many designs. It's a really useful process to optimize panel
>> > utilization and sometimes assy tooling/depaneling tradeoffs. However,
>our
>> > experience here shows your concerns are valid. I suggest the even
>bigger
>> > concern should be the risk of latent defects that will pass through all
>> > your tests and into the field.
>> >
>> > We've seen the risk to be with ceramic chip components (chip caps et al)
>> > within .1 - .2" of the score. The mode is latent ceramic cracking
>leading
>> > to leakages or outright device failure. Either way the end result is
>the
>> > same -- field infant mortality.
>> >
>> > As a result of our experience (read scar tissue -- and some crude long
>> > forgotten rel experiments way back in the early 90's dark ages -- Phil
>> > Bavaro may have better memory of that) our design rules don't allow
>scoring
>> > if chip components are within 0.200" of the score. The exception to the
>> > rule we sometimes make is when the assembly has shields soldered out to
>> > board edge effectively making a box beam that stops/reduces flex of the
>> pwb.
>> >
>> > I'd be real interested to hear what others have learned and design rules
>> > they maintain -- esp if there's been some science applied to their
>> > establishing their rules.
>> >
>> > Dwight
>> >
>> > At 11:01 AM 6/1/00 -0400, Ed Holton wrote:
>> > >We have recently started using boards with V-score for the
>> panelization and
>> > >we have a debate raging here. There is a concern about separating the
>> > >boards before versus after the incircuit test and whether there is the
>> > >possibility that there is imparted stress to the board that could
>create a
>> > >failure mechanism that might have been caught at the ICT and not at the
>> > >functional test, thus the requirement to singulate before versus after
>> ICT.
>> > >I have read various articles, but am wondering what people have found
>in
>> > >the real world.
>> > >
>> > >Thanks
>> > >
>> > >Ed Holton
>> > >Manufacturing Engineer and Group Leader
>> > >Hella Electronics
>> > >Telephone (734) 414-0944
>> > >Fax (734) 414-0941
>> > >
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Martin Christie
ACW Technology Ltd.,
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