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June 2000

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Subject:
From:
Steve Kingdon <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Fri, 16 Jun 2000 12:17:21 +1200
Content-Type:
text/plain
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text/plain (105 lines)
Hi Craig,

How's it going?

I found the answer to your question in the Designer Council archives.....I
am
assuming this guy knows what he is talking about. (sorry to whoever posted
this!)

quote "A. Paper doll placement strategy is where you make one to one scaled
boxes
of the outer parameters (including pick and place clearances) of each
component or part to determine if the space allocated is sufficient for
parts placement over the entire PCB." end quote

I could not find any reference to it in the Study guide or IPC-2221. My
guess it
should be somewhere under IPC-2221 Section 3.6.2. Feasibility Density
Evaluation.
The term itself could be in IPC-T-50, Term and Definitions for
Interconnecting and
Packaging Electronic Circuits, however we do not have this standard.

A long list of explanations for non obvious topics was posted, as well as a
response
from Gary Ferrari as to the purpose of the Appendix A, i.e. they are not
questions,
but objectives to be understood on a specific topic.

Go to the IPC Designer Council archives at www.ipc.org, and search on "paper
doll".

Do you subscribe to the IPC Designer Council forum? It may be more
appropriate (for a PCB
designer) to ask for advice on certification in that forum.

I am also doing this course, so see you on the 26th. Good luck with the
study.

Steve.

> Steve Kingdon
> PCB Designer
> ----------------------------------------------------------------------
> ------------------
> Invensys Energy Systems (NZ) Limited, 39 Princess St, PO Box 11-188
> Christchurch 8030, New Zealand
> Phone: (++64) 3 343-3314, Fax: (++64) 3 343 5100
> DDI:   (++64) 3 <343 7440 ext 8401>
> Email: [log in to unmask]
> Website: http://www.invensys-energy.co.nz
>


-----Original Message-----
From: Craig Mcglinchy [mailto:[log in to unmask]]
Sent: Friday, 16 June 2000 09:51
To: [log in to unmask]
Subject: [TN] IPC designer certification - Paper Doll


I am studying towards my IPC designer certification. In the syllabus one
of the objectives is to explain the paper doll placement strategy. I am
not familiar with this stratgey, could someone please explain this to
me.
If anyone has any other advice about the certification, I would really
appreciate this.

Thanks in advance

Craig McGlinchy
PCB Designer
Tait Electronics Ltd
Ph. (64) 3 357-0779
Fax (64) 3 358-0432

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