A NASA space engineer asking for crack origin! Ouff, felt chills up and down. I use sometimes refer to NASA's skill and reporting when something is tricky HiTech. So, they are not immortals...the time I had little experience myself I used to read every NASA article that happened to pass here, long before the web age, wasn't so easy to get material from them. NASA people were those who decided that three molecular layers of water was the limit for humidity on an encapsulated chip (TO-5 etc), which in turn resulted in the Helium-leakage measuring philosophy.And other stuff that ended in known norms.... Now, cracks in the GaAs chips has been up sometimes when one can't explain GaAs chip anomalies, especially the large chips like MMICs. These are thinned down to some 100 microns in thickness, which does not make the situation better. And so you may also have a lot of vias to ground lined neatly in a row from one chip end to the other. This acts like what you do when you cut a!
glass sheet: if a crack occurs in one end it may propagate via the via holes. Further to the nature of Jong's question, we can as well add the contradictions. GaAs is a brittle material, and most books underline the importance of matching as good as possible. We use also CuW or similar materials. And still you hear about people that mounted on pure Copper without cracked chips! One author described mounting of 12x12 mm GaAs chips on Cu, tempcycled and performed other environmental tests withour cracks. How come? The answer seems to be the choice of attaching material and method. The solidification rate has to be chosen such that you build in as little tension as possible. Or you may use DIEMAT materials or other polymer based metalfilled adhesives (hundreds of formulaes). Finally, cracking has not been reported here as a primary failure when chips behave bad, maybe thanks to the careful design of the vacuum soldering process, which is done in a number of temperature steps.
So many words without saying anything essential. Hmm...I have to agree with Mike Fenner, you may also see to other things like metallisation etc. Before I stop babbling, I recommend you to inspect the p-a-p vacuum collet (or what you use). If the tool uses too much force, and hurt the chip edge, one can get weak points that become the start of cracking. And ask yourself if the cracks are possibly only in the passivation, then you may have another type of problem: a wafer manufacturing process problem. I stop here before I get a tomatoe coming from the fiber, but will add more lately if needed.
May I ask you what chip maker you use? TQT, NEC, NG, UMS..or what? They have different processes. And, do you make further analysis than just look at the chips?
Ingemar Hernefjord
Ericsson Microwave Systems
-----Original Message-----
From: jong s kadesch [mailto:[log in to unmask]]
Sent: den 12 juni 2000 15:38
To: [log in to unmask]
Subject: [TN] GaAs Cracks
Hi Technetters,
Recently, I have attached GaAs die on a CVD diamond substrate using 80/20
Au/Sn eutectic preform. After the die bonding at 280 C, we found cracks
(mostly 90 degrees and 45 degrees cracks) on the surface of the GaAs during
the inspection. We suspect that it is due to TCE mismatch or thermal
shock. We are thinking about using different die attach material that
requires lower temperature process. Anyone has advise, suggestion, or any
experience similar to this? Thanks.
Jong S. Kadesch
Sr. Engineer
NASA-GSFC/Orbital Sciences Corp.
562/Component Technologies and Radiation Branch
Greenbelt, MD 20771
tel:(301)286-2785
fax:(301)286-1695
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