Jong,

I am not exactly sure how to interpret the 45 and 90° cracks (with respect
to what surface/axis?), but my ball park figure of merit for GaAs' TCE is
6-6.5 PPM.  For diamond - around 3.5-4PPM.

So yes, you would appear to have a 2.5-3PPM/°C TCE differential - with the
chip attempting to shrink more than the substrate during cooling, you could
end up with tensile stress within the chip itself - hence cracks, which I
would assume to propagate from the center of the chip vertically downwards
or downward and out in a conical fashion, sort of like an inverted ice cream
cone.

How about using a CuW or AlSiC substrate/tab.  You could taylor the TCE to
match your requirements - maybe giving up thermal conductivity a little?

Steve Creswick






At 09:37 AM 6/12/00 -0400, you wrote:
>Hi Technetters,
>
>Recently, I have attached GaAs die on a CVD diamond substrate using 80/20
>Au/Sn eutectic preform.  After the die bonding at 280 C, we found cracks
>(mostly 90 degrees and 45 degrees cracks) on the surface of the GaAs during
>the inspection.  We suspect that it is due to TCE mismatch or thermal
>shock.  We are thinking about using different die attach material that
>requires lower temperature process.  Anyone has advise, suggestion, or any
>experience similar to this?  Thanks.
>
>
>Jong S. Kadesch
>Sr. Engineer
>NASA-GSFC/Orbital Sciences Corp.
>562/Component Technologies and Radiation Branch
>Greenbelt, MD 20771
>tel:(301)286-2785
>fax:(301)286-1695
>
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