Being one of John Maxwell's "fans" I recommend his articles about design for
manufacturability . Concerning chip capacitors, we follow as much as possible the rules
, and Dwight's comments are in this spirit. Most of the failures we also encountered
were with chip capacitors, and the separation method , the distance from the edge, and
the orientation of the chip were the culprits, alone or in combination. We had for
instance one panel with circuits which were manufactured first as single, then as 4 in
panel. Due to the proximity of the chip cap to the edge, we had failures after
separation, and had to change the artwork accordingly.
Gaby

Dwight Mattix wrote:

> We score many designs.  It's a really useful process to optimize panel
> utilization and sometimes assy tooling/depaneling tradeoffs.  However, our
> experience here shows your concerns are valid.  I suggest the even bigger
> concern should be the risk of latent defects that will pass through all
> your tests and into the field.
>
> We've seen the risk to be with ceramic chip components (chip caps et al)
> within .1 - .2" of the score.  The mode is latent ceramic cracking leading
> to leakages or outright device failure.  Either way the end result is the
> same -- field infant mortality.
>
> As a result of our experience (read scar tissue -- and some crude long
> forgotten rel experiments way back in the early 90's dark ages -- Phil
> Bavaro may have better memory of that) our design rules don't allow scoring
> if chip components are within 0.200" of the score. The exception to the
> rule we sometimes make is when the assembly has shields soldered out to
> board edge effectively making a box beam that stops/reduces flex of the pwb.
>
> I'd be real interested to hear what others have learned and design rules
> they maintain -- esp if there's been some science applied to their
> establishing their rules.
>
> Dwight
>
> At 11:01 AM 6/1/00 -0400, Ed Holton wrote:
> >We have recently started using boards with V-score for the panelization and
> >we have a debate raging here.  There is a concern about separating the
> >boards before versus after the incircuit test and whether there is the
> >possibility that there is imparted stress to the board that could create a
> >failure mechanism that might have been caught at the ICT and not at the
> >functional test, thus the requirement to singulate before versus after ICT.
> >I have read various articles, but am wondering what people have found in
> >the real world.
> >
> >Thanks
> >
> >Ed Holton
> >Manufacturing Engineer and Group Leader
> >Hella Electronics
> >Telephone (734) 414-0944
> >Fax (734) 414-0941
> >
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