TECHNET Archives

April 2000

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Stuart Chessen <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Thu, 6 Apr 2000 08:09:00 -0800
Content-Type:
text/plain
Parts/Attachments:
text/plain (104 lines)
All welcome

Silicon Valley Chapter Meeting!

Date:          April 13, 2000

Factory Tour and Speaker:
~ AGENDA ~

5:00 - 5:30 p.m.                                Sign-In
5:30 - 6:30 p.m.                              "Factory Tour"
6:30 - 7:30 p.m.                                Dinner
7:30 - 8:30 p.m.          "Optimization of Printing Process for CSP Assemblies"


~ REGISTRATION FEES ~

Members with reservations     $10          Non-members with reservations     $15
Members without reservations     $10          Non-members without reservations
$15


~ MENU ~     Hawaiian Luau Buffet


Factory Tour: Photo Etch, Stencil Manufacturing
Providing an Intro. of Photo Etch Technology, Dinner and a Tour of their
facility!

Photo Etch Technology is a leading manufacturer of Solder Paste Stencils.
Nationally Headquartered in Lowell, MA, it has satellite facilities in
Clearwater, FL, Releigh, NC and Santa Clara, CA.  Photo Etch has been a
manufacturer of stencils for over ten years.  The facility in Santa Clara uses
laser technology exclusively for the manufacturing of state of the art stencils.
Please join us on Thursday, April 13th, 2000 for dinner and a plant tour.  RSVP
by April 10th to Amy Driban via fax at (408) 265-1305.

Location:   Photo Etch Technology,  3014 Scott Blvd.  (408) 988-0220, Santa
Clara, CA   95054

DIRECTIONS:
From Highway 101 exit at San Thomas Expressway to Scott Blvd.  Take a left onto
Scott Blvd, Photo Etch is approximately 1/4 mile on the right in the Pacific
Gulf Properties.  We are in unit 3014 in this complex.

Speaker:  " Optimization of the Printing Process for CSP Assemblies"
Sammy Yi, Technical Director,   Flextronics International, Inc.

Sammy Yi, is the Technical Director for Flextronics International, Inc.
Currently responsible for company wide advanced manufacturing process
development and implementation. Prior to Flextronics, Sammy had over 10 years
experience in electronics manufacturing. He has worked in both OEM and EMS
companies, such as GSS/ARRAY Technology, Adaptec, Manufacturer's Services, and
Venture Manufacturing. He had wide range of responsibilities in engineering
management, quality system, process development and operations management. Sammy
has been president of SMTA for Silicon Valley Chapter for last three years.

"Optimization of the Printing Process for CSP Assembly"
Abstract:  Smaller area array packages, such as mBGAs and CSPs are gaining in
popularity by providing high package density with the smallest possible package
size. These small area array packages require smaller pitch and pad size. For
some CSPs, the ball pitch can be less than 20 mils and the pad size less than 10
mils, which makes the solder paste printing process difficult.  It is important
to understand the variables that affect the printing process and quality when
identifying printing process capabilities and finding the optimum solution for a
small area array package.

Many factors affect solder paste printing capability and quality, such as the
stencil, solder paste type, printed circuit board and solder paste printing
process. Within these categories, there are many variables. The stencil, for
instance, can vary in thickness, aperture opening, aperture shape, aspect ratio
limitation, stencil fabrication and surface polish methods, stencil fabrication
accuracy, etc.

The purpose of this study is to investigate solder paste printing capabilities
and limitations with a focus on small area array packages.  This paper will
identify the critical variables that affect the solder printing process and
divide them into two groups. In order to measure the interaction among these
variables, two separate designs of experiment (DOE) were conducted.  This paper
will discuss the method of the DOEs, as well as the relationships among the
variables. Finally, this study will describe the optimum conditions for solder
paste printing and present design guidelines for manufacturing small area array
packages.

Reservations:     Contact Amy Driban via fax at (408) 265-1305.  Make your
reservation before 12:00 p.m., Monday, April 10, 2000.

Please treat your reservation as a commitment.  No-shows will be invoiced.
Please cancel your reservation by noon on Wednesday, April 12, 2000.

##############################################################
TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
##############################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in
the body:
To subscribe:   SUBSCRIBE TECHNET <your full name>
To unsubscribe:   SIGNOFF TECHNET
##############################################################
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
information.
If you need assistance - contact Keach Sasamori at [log in to unmask] or
847-509-9700 ext.5315
##############################################################

ATOM RSS1 RSS2