Hi Werner,
Sorry bout the lack of info. My mistake. To recap, we had some parts fail
our internal test for voids in the .0135 vias. The parts that passed our
electrical test at 100 volts shipped. We assembled the parts found some
additional failures after assembly. Analysis of the failed assembly revealed
that the failure was due to a marginal internal interconnect related to
drill debris. We concluded that the majority of the lot was good but had no
way of sorting for this defect. Due to the amount of money already invested
we did not want scrap good parts but also did not want to ship marginal
parts to the customer. So we devised a plan to instill some confidence in
the products that passed test. We obtain the end customers approval and
proceeded as follows.
1. We subjected all parts to an outside thermal stress
cycling as outlined in IPC TM 2.6.6. There are four
cycles outlined in this test ( not 3 as previously noted).
The intent here was
induce failure on any marginal interconnects.We
tested to class A as follows.
Cycle 1 is 125 Deg, C for 30 minutes
Cycle 2 is 25 Deg. C for 10-15 minutes
Cycle 3 is -65 Deg. C for 30 minutes
Cycle 4 is 25 Deg. C for 10-15 minutes
2. We then finished assembling the parts. due to the
parts being double sided, the parts were processed
through two convection oven reflow processes.
3. We then performed an in circuit test. Those that
passed were then burned in. Then they were tested at
final test after burn in.
This was the last test on our plan. However, out of curiosity, we sent 6
parts that have passed all the testing noted above out for the same thermal
cycle again. All 6 parts failed. We have not determined the cause as yet.
Our test engineers haven't gotten to them. The primary question here is
related to this type of thermal stress testing on assembled parts. We are
not sure if this test is designed for assembled parts. We do not know if the
soldered joints or components are designed to withstand this test. So, do
you think we are over testing?
----- Original Message -----
From: "Werner Engelmaier" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Saturday, April 01, 2000 12:20 AM
Subject: Re: [TN] Thermal stressing
> Hi Ed,
> You are giving us very little to go on. You do not even say whether the
> "interconnects" you have problems with are SJs or PTH/PTVs.
> >We had some concerns about marginal interconnects on some 10 layer boards
> >that had passed the bare printed circuit board bed of nails test at 100
> >volts.
> This would indicate PTH/PTVs as your problems, but bare board bed-of-nails
> testing does not give you any idea whether your board can survive
soldering
> operations.
> >To instill more confidence in the products, the bare printed circuit
boards
> were >submitted for environmental chamber thermal stressing (the 3 cycle
test
> as outlined >by IPC).
> What "3 cycle test as outlined by IPC" are youtalking about? I am not
aware
> of any such test, and I have been involved in IPC a loooooong time.
> >Parts were stressed by an outside lab, returned, assembled, in circuit
> tested, burned >in, then final tested. A sample of the parts that passed
the
> final assembly test was >sent out again for the environmental chamber
stress
> test. The parts were then >retested and all the parts failed test. ( We
have
> not determined why yet.)
> What "environmental chamber stress test"? Temperatures? Cycles? Shock?
> >Based on this I have two questions.
> >1) Is it possible to overstress loaded board?
> Answer: Absolutely.
> >2) Would you expect assembled boards to pass after chamber thermal
cycling?
> That all depends on the details! Properly designed and built assemblies
pass
> chamber thermal cycling all the time.
>
> Werner Engelmaier
> Engelmaier Associates, L.C.
> Electronic Packaging, Interconnection and Reliability Consulting
> 7 Jasmine Run
> Ormond Beach, FL 32174 USA
> Phone: 904-437-8747, Fax: 904-437-8737
> E-mail: [log in to unmask], Website: www.engelmaier.com
>
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